On-off keying using vector modulation
First Claim
1. A method comprising:
- deriving a subcarrier frequency from a binary data stream having a clock frequency, wherein the subcarrier frequency is substantially the same as the clock frequency;
gating the subcarrier frequency using the data stream to produce a modulated on-off keying signal;
delaying the modulated on-off keying signal relative to the binary data stream by a predetermined amount to produce a delayed modulated on-off keying signal; and
conditioning the modulated on-off keying signal and the delayed modulated on-off keying signal to create a differential transition signal in an in-phase channel and a quadrature-phase channel to provide a stable amplitude signal level reference at an input to an in-phase and quadrature-phase vector modulator.
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Accused Products
Abstract
A system and method including deriving a subcarrier frequency from a binary data stream having a clock frequency, wherein the subcarrier frequency is substantially the same as the clock frequency; gating the subcarrier frequency using the data stream to produce a modulated OOK signal; determining a OOK subcarrier center frequency based on the modulated OOK signal with the clock frequency; delaying the modulated OOK signal relative to the binary data stream by a predetermined amount to produce a delayed modulated OOK signal; conditioning the modulated OOK signal and the delayed modulated OOK signal to create a differential transition signal in an I channel and a Q channel to provide a stable amplitude signal level reference at an input to an I and Q vector modulator.
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Citations
10 Claims
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1. A method comprising:
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deriving a subcarrier frequency from a binary data stream having a clock frequency, wherein the subcarrier frequency is substantially the same as the clock frequency; gating the subcarrier frequency using the data stream to produce a modulated on-off keying signal; delaying the modulated on-off keying signal relative to the binary data stream by a predetermined amount to produce a delayed modulated on-off keying signal; and conditioning the modulated on-off keying signal and the delayed modulated on-off keying signal to create a differential transition signal in an in-phase channel and a quadrature-phase channel to provide a stable amplitude signal level reference at an input to an in-phase and quadrature-phase vector modulator.
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2. A device comprising:
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means for deriving a subcarrier frequency from a binary data stream having a clock frequency, wherein the subcarrier frequency is substantially the same as the clock frequency; means for gating the subcarrier frequency using the data stream to produce a modulated on-off keying signal; means for delaying the modulated on-off keying signal relative to the binary data stream by a predetermined amount to produce a delayed modulated on-off keying signal; and means for conditioning the modulated on-off keying signal and the delayed modulated on-off keying signal to create a differential transition signal in an in-phase channel and a quadrature-phase channel to provide a stable amplitude signal level reference at an input to an in-phase and quadrature-phase vector modulator.
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3. A method comprising:
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separating a binary data stream into a clock signal and a data signal; producing a plurality of clock signals and a plurality of data signals from the clock signal and the data signal; gating the plurality of clock signals using the plurality of data signals to produce a plurality of on-off keying modulated signals; delaying two or more of the plurality of on-off keying modulated signals to create a first set of on-off keying modulated signals and a second set of on-off keying modulated signals wherein the first set of on-off keying modulated signals has a 90 degree phase lag with respect to the second set of on-off keying modulated signals. - View Dependent Claims (4, 5, 6)
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7. A device comprising:
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means for separating a binary data stream into a clock signal and a data signal; means for producing a plurality of clock signals and a plurality of data signals from the clock signal and the data signal; means for gating the plurality of clock signals using the plurality of data signals to produce a plurality of on-off keying modulated signals; and means for delaying two or more of the plurality of on-off keying modulated signals to create a first set of on-off keying modulated signals and a second set of on-off keying modulated signals wherein the first set of on-off keying modulated signals has a 90 degree phase lag with respect to the second set of on-off keying modulated signals. - View Dependent Claims (8, 9, 10)
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Specification