Large multiplier for programmable logic device
First Claim
1. A specialized processing block for a programmable logic device, said specialized processing block comprising:
- a plurality of multipliers; and
circuitry for adding and/or subtracting and/or accumulating outputs of said multipliers;
wherein;
at least one of said multipliers has a respective sign control input associated with at least one respective multiplicand input thereof, to which a signal is applied that controls whether said respective multiplicand input is treated as signed or unsigned;
said specialized processing block further comprising;
a selector at each said sign control input that controllably selects between a first signal that forces said multiplicand input to be unsigned and a second signal that indicates whether said multiplicand input is signed or unsigned, in response to a control signal separate from said first signal and from said second signal.
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Accused Products
Abstract
A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks. Circuitry that controls when an input is signed or unsigned facilitates complex arithmetic.
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Citations
5 Claims
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1. A specialized processing block for a programmable logic device, said specialized processing block comprising:
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a plurality of multipliers; and circuitry for adding and/or subtracting and/or accumulating outputs of said multipliers;
wherein;at least one of said multipliers has a respective sign control input associated with at least one respective multiplicand input thereof, to which a signal is applied that controls whether said respective multiplicand input is treated as signed or unsigned;
said specialized processing block further comprising;a selector at each said sign control input that controllably selects between a first signal that forces said multiplicand input to be unsigned and a second signal that indicates whether said multiplicand input is signed or unsigned, in response to a control signal separate from said first signal and from said second signal. - View Dependent Claims (2, 3, 4, 5)
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Specification
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- Resources
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Current AssigneeAltera Corporation (Intel Corporation)
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Original AssigneeAltera Corporation (Intel Corporation)
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InventorsLanghammer, Martin, Tharmalingam, Kumara
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Primary Examiner(s)Ngo, Chuong D
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Application NumberUS11/682,787Time in Patent Office2,184 DaysField of Search708/620, 708/625, 708/622US Class Current708/620CPC Class CodesG06F 17/10 Complex mathematical operat...G06F 7/5324 partitioned, i.e. using rep...
