Apparatus and method for multi-level cache utilization

• US 8,386,701 B2
• Filed: 04/19/2012
• Issued: 02/26/2013
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Tetrick, Raymond Scott, Juenemann, Dale, Brennan, Robert
• Primary Examiner(s): Thai, Tuan
• Assistant Examiner(s): LI, ZHUO H
• Application Number:
  US13/450,882
• Publication Number:
  US 20120203960A1
• Time in Patent Office: 313 Days
• Field of Search: 711/1, 711/36, 711/103, 711/113, 711/118, 711/119, 711/122, 711/126, 711/137
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory. Other embodiments are disclosed and claimed.

Claims

1. A processor-based system, comprising:

a processor;

a system memory coupled to the processor;

a mass storage device;

a multi-level non-volatile cache memory located between the system memory and the mass storage device, wherein the multi-level non-volatile cache memory includes a plurality of non-volatile cache memories, wherein each non-volatile cache memory of the plurality of non-volatile cache memories has an operating characteristic, wherein the operating characteristics among the plurality of non-volatile cache memories are different and wherein each non-volatile cache memory of the plurality of non-volatile cache memories has a cache insertion policy based on its operating characteristic, and wherein the cache insertion policies among the plurality of non-volatile cache memories are different; and

code stored on the processor-based system to cause the processor-based system to, in response to a request for access to information on the mass storage device, cache the information in one of the plurality of non-volatile cache memories in accordance with the plurality of cache insertion policies.

2. The system of claim 1, wherein the plurality of non-volatile cache memories have different speeds.

3. The system of claim 1, wherein the plurality of non-volatile cache memories have different storage densities.

4. A storage system comprising:

a system memory;

a mass storage device;

a multi-level non-volatile cache memory located between the system memory and the mass storage device, wherein the multi-level non-volatile cache memory includes a plurality of non-volatile cache memories, wherein each non-volatile cache memory has an operating characteristic, and wherein the operating characteristics among the plurality of non-volatile cache memories are different; and

a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory in accordance with the operating characteristics of the plurality of non-volatile cache memories,

wherein each non-volatile cache memory of the plurality of non-volatile cache memories has a cache insertion policy, wherein the cache insertion policies among the plurality of non-volatile cache memories are different, and wherein the controller is configured to implement the cache insertion policies.

5. The storage system of claim 4, wherein the plurality of non-volatile cache memories have different speeds.

6. The system of claim 4, wherein the plurality of non-volatile cache memories have different storage densities.

7. A computer-implemented method of utilizing a multi-level non-volatile cache memory, the method comprising:

receiving a request for access to information on a mass storage device;

caching the information in one of a plurality of non-volatile cache memories of a multi-level non-volatile cache memory, wherein each non-volatile cache memory of the multi-level non-volatile cache memory has an operating characteristic, wherein the operating characteristics among the plurality of non-volatile cache memories of multi-level non-volatile cache memory are different, wherein each non-volatile cache memory has a cache insertion policy based on its operating characteristic, and wherein the cache insertion policies among the plurality of non-volatile cache memories are different wherein the caching is in accordance with a plurality of cache insertion policies.

8. The computer-implemented method of claim 7, wherein the plurality of non-volatile cache memories have different speeds.

9. The computer-implemented method of claim 7, wherein the plurality of non-volatile cache memories have different storage densities.