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Apparatus and method for multi-level cache utilization

  • US 8,386,701 B2
  • Filed: 04/19/2012
  • Issued: 02/26/2013
  • Est. Priority Date: 06/30/2008
  • Status: Active Grant
First Claim
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1. A processor-based system, comprising:

  • a processor;

    a system memory coupled to the processor;

    a mass storage device;

    a multi-level non-volatile cache memory located between the system memory and the mass storage device, wherein the multi-level non-volatile cache memory includes a plurality of non-volatile cache memories, wherein each non-volatile cache memory of the plurality of non-volatile cache memories has an operating characteristic, wherein the operating characteristics among the plurality of non-volatile cache memories are different and wherein each non-volatile cache memory of the plurality of non-volatile cache memories has a cache insertion policy based on its operating characteristic, and wherein the cache insertion policies among the plurality of non-volatile cache memories are different; and

    code stored on the processor-based system to cause the processor-based system to, in response to a request for access to information on the mass storage device, cache the information in one of the plurality of non-volatile cache memories in accordance with the plurality of cache insertion policies.

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