Stacked DIMM memory interface

• US 8,386,722 B1
• Filed: 06/23/2008
• Issued: 02/26/2013
• Est. Priority Date: 06/23/2008
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Wang, David T., Rajan, Suresh Natarajan
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US12/144,396
• Time in Patent Office: 1,709 Days
• Field of Search: None
• US Class Current: 711/154
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

One embodiment of the present invention sets forth an interface circuit configured to combine time staggered data bursts returned by multiple memory devices into a larger contiguous data burst. As a result, an accurate timing reference for data transmission that retains the use of data (DQ) and data strobe (DQS) signals in an infrastructure-compatible system while eliminating the cost of the idle cycles required for data bus turnarounds to switch from reading from one memory device to reading from another memory device, or from writing to one memory device to writing to another memory device may be obtained, thereby increasing memory system bandwidth relative to the prior art approaches.

Claims

1. An interface circuit configured to re-time a plurality of data bursts returned by a plurality of memory devices to obtain a contiguous data burst, the interface circuit comprising:

a system control signal interface adapted to receive a first command from a memory controller;

an intelligent bufer chip; and

emulation and command translation logic adapted to;

translate a first address associated with the first command,

issue the first command to a first memory device within the plurality of memory devices corresponding to the first address,

determine that the first command is a read command,

select a memory data signal interface corresponding to the first memory device,

receive a first data burst from the first memory device,

delay the first data burst to eliminate a first clock-to-data phase between the first memory device and the interface circuit, and

re-drive the first data burst to the memory controller,

wherein the plurality of memory devices are arranged in a stack, and the interface circuit is integrated within the stack, and

wherein the plurality of the memory devices comprises dynamic random access memories, and the intelligent buffer chip and the dynamic random access memories are included in a dual in-line module.

2. The interface circuit of claim 1, wherein:

the system control signal interface is further adapted to receive a second command from the memory controller; and

the emulation and command translation logic is further adapted to;

translate a second address associated with the second command,

issue the second command to a second memory device within the plurality of memory devices corresponding to the second address,

determine that the second command is a read command,

select a memory data signal interface corresponding to the second memory device,

receive a second data burst from the second memory device,

delay the second data burst to eliminate a second clock-to-data phase between the second memory device and the interface circuit, and

re-drive the second data burst to the memory controller so that the first data burst and the second data burst are combined into a third data burst that is contiguous.

3. The interface circuit of claim 2, further comprising a means for determining optimized timing for re-driving the first data burst and the second data burst to eliminate idle cycles between the first data burst and the second data burst.

4. The interface circuit of claim 3, further comprising scheduling logic configured to order and concatenate the first and second data bursts.

5. The interface circuit of claim 4, wherein the scheduling logic is implemented using registers, multiplexors, and combination logic.

6. The interface circuit of claim 2, wherein:

the system control signal interface is further adapted to receive a third command from the memory controller;

the emulation and command translation logic is further adapted to;

translate a third address associated with the third command,

issue the third command to a third memory device within the plurality of memory devices corresponding to the third address,

determine that the third command is a write command,

select a memory data signal interface corresponding to the third memory device,

receive a third data burst from the memory controller; and

the memory data signal interface corresponding to the third memory device is adapted to;

delay the third data burst to eliminate a third clock-to-data phase between the third memory device and the interface circuit, and

re-drive the third data burst to the third memory device.

7. The interface circuit of claim 6, further comprising initialization and configuration logic, wherein:

the system control signal interface is further adapted to receive a fourth command from the memory controller;

the emulation and command translation logic is further adapted to determine that the fourth command is a calibration command; and

the initialization and calibration logic is adapted to;

perform calibration sequence to determine the first, second, and third clock-to-data phases,

based on the first clock-to-data phase, set a first delay adjustment within the memory data signal interface corresponding to the first memory device,

based on the second clock-to-data phase, set a second delay adjustment within the memory data signal interface corresponding to the second memory device, and

based on the third clock-to-data phase, set a third delay adjustment within the memory data signal interface corresponding to the third memory device.

8. The interface circuit of claim 7, wherein each of the first, second, and third clock-to-data phases includes and clock-to-data (clock-to-DQ) value and a clock-to-data strobe signal (clock-to-DQS) value.

9. The interface circuit of claim 1, further comprising a memory address signal interface, a memory control signal interface, a memory clock signal interface, a system address signal interface, a system clock signal interface, and a system data signal interface.

10. The interface circuit of claim 1, wherein the emulation and command translation logic is programmed to emulate an interface protocol associated with each memory device within the plurality of memory devices.

11. The interface circuit of claim 1, wherein one or more memory devices within the plurality of memory devices are arranged a stack.

12. The interface circuit of claim 1, wherein each memory device within the plurality of memory devices comprises a dynamic random access memory chip.

13. The interface circuit of claim 1, wherein the interface circuit is coupled directly to a memory module.

14. The interface circuit of claim 13, wherein the memory module comprises a dual in-line memory module.

15. The interface circuit of claim 1, wherein the interface circuit is connected to a circuit board.

16. The interface circuit of claim 1, wherein the interface circuit is included within a computing device.

17. An apparatus comprising:

a plurality of memory devices;

a memory controller; and

an interface circuit electrically connected to the plurality of memory devices and the memory controller and configured to re-time a plurality of data bursts returned by the plurality of memory devices to obtain a contiguous data burst, wherein the interface circuit comprises;

a system control signal interface adapted to receive a first command from the memory controller;

an intelligent buffer chip; and

emulation and command translation logic adapted to;

translate a first address associated with the first command,

issue the first command to a first memory device within the plurality of memory devices,

determine that the first command is a read command,

select a memory data signal interface corresponding to the first memory device,

receive a first data burst from the first memory device,

delay the first data burst to eliminate a first clock-to-data phase between the one of the first memory device and the interface circuit, and

re-drive the first data burst to the memory controller,

wherein the plurality of memory devices are arranged in a stack, and the interface circuit is integrated within the stack, and

wherein the plurality of the memory devices comprises dynamic random access memories, and the intelligent buffer chip and the dynamic random access memories are included in a dual in-line memory module.

18. The apparatus of claim 17 further comprising a motherboard.

19. The apparatus of claim 18, further comprising a platform chassis.

20. An interface circuit configured to re-time a plurality of data bursts returned by a plurality of memory devices to obtain a contiguous data burst, the interface circuit comprising:

a system control signal interface adapted to receive a first command from a memory controller;

emulation and command translation logic adapted to;

translate a first address associated with the first command;

issue the first command to a first memory device within the plurality of memory devices corresponding to the first address;

determine that the first command is a read command;

select a memory data signal interface corresponding to the first memory device;

receive a first data burst from the first memory device;

delay the first data burst to eliminate a first clock-to-data phase between the first memory device and the interface circuit, and

re-drive the first data burst to the memory controller; and

initialization and configuration logic,

wherein the system control signal interface is further adapted to receive a second command from the memory controller, and the emulation and command translation logic is further adapted to;

translate a second address associated with the second command,

issue the second command to a second memory device within the plurality of memory devices corresponding to the second address,

determine that the second command is a read command,

select a memory data signal interface corresponding to the second memory device,

receive a second data burst from the second memory device,

delay the second data burst to eliminate a second clock-to-data phase between the second memory device and the interface circuit, and

re-drive the second data burst to the memory controller so that the first data burst and the second data burst are combined into a third data burst that is contiguous;

wherein the system control signal interface is further adapted to receive a third command from the memory controller, and the emulation and command translation logic is further adapted to;

translate a third address associated with the third command,

issue the third command to a third memory device within the plurality of memory devices corresponding to the third address,

determine that the third command is a write command,

select a memory data signal interface corresponding to the third memory device,

receive a third data burst from the memory controller; and

the memory data signal interface corresponding to the third memory device is adapted to;

delay the third data burst to eliminate a third clock-to-data phase between the third memory device and the interface circuit, and

re-drive the third data burst to the third memory device;

wherein the system control signal interface is further adapted to receive a fourth command from the memory controller, and the emulation and command translation logic is further adapted to determine that the fourth command is a calibration command; and

the initialization and calibration logic is adapted to;

perform calibration sequence to determine the first, second, and third clock-to- data phases,

based on the first clock-to-data phase, set a first delay adjustment within the memory data signal interface corresponding to the first memory device,

based on the second clock-to-data phase, set a second delay adjustment within the memory data signal interface corresponding to the second memory device, and

based on the third clock-to-data phase, set a third delay adjustment within the memory data signal interface corresponding to the third memory device.

21. The interface circuit of claim 20, wherein each of the first, second, and third clock-to-data phases includes and clock-to-data (clock-to-DQ) value and a clock-to-data strobe signal (clock-to-DQS) value.