Stacked DIMM memory interface
First Claim
1. An interface circuit configured to re-time a plurality of data bursts returned by a plurality of memory devices to obtain a contiguous data burst, the interface circuit comprising:
- a system control signal interface adapted to receive a first command from a memory controller;
an intelligent bufer chip; and
emulation and command translation logic adapted to;
translate a first address associated with the first command,issue the first command to a first memory device within the plurality of memory devices corresponding to the first address,determine that the first command is a read command,select a memory data signal interface corresponding to the first memory device,receive a first data burst from the first memory device,delay the first data burst to eliminate a first clock-to-data phase between the first memory device and the interface circuit, andre-drive the first data burst to the memory controller,wherein the plurality of memory devices are arranged in a stack, and the interface circuit is integrated within the stack, andwherein the plurality of the memory devices comprises dynamic random access memories, and the intelligent buffer chip and the dynamic random access memories are included in a dual in-line module.
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Accused Products
Abstract
One embodiment of the present invention sets forth an interface circuit configured to combine time staggered data bursts returned by multiple memory devices into a larger contiguous data burst. As a result, an accurate timing reference for data transmission that retains the use of data (DQ) and data strobe (DQS) signals in an infrastructure-compatible system while eliminating the cost of the idle cycles required for data bus turnarounds to switch from reading from one memory device to reading from another memory device, or from writing to one memory device to writing to another memory device may be obtained, thereby increasing memory system bandwidth relative to the prior art approaches.
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Citations
21 Claims
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1. An interface circuit configured to re-time a plurality of data bursts returned by a plurality of memory devices to obtain a contiguous data burst, the interface circuit comprising:
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a system control signal interface adapted to receive a first command from a memory controller; an intelligent bufer chip; and emulation and command translation logic adapted to; translate a first address associated with the first command, issue the first command to a first memory device within the plurality of memory devices corresponding to the first address, determine that the first command is a read command, select a memory data signal interface corresponding to the first memory device, receive a first data burst from the first memory device, delay the first data burst to eliminate a first clock-to-data phase between the first memory device and the interface circuit, and re-drive the first data burst to the memory controller, wherein the plurality of memory devices are arranged in a stack, and the interface circuit is integrated within the stack, and wherein the plurality of the memory devices comprises dynamic random access memories, and the intelligent buffer chip and the dynamic random access memories are included in a dual in-line module. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. An apparatus comprising:
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a plurality of memory devices; a memory controller; and an interface circuit electrically connected to the plurality of memory devices and the memory controller and configured to re-time a plurality of data bursts returned by the plurality of memory devices to obtain a contiguous data burst, wherein the interface circuit comprises; a system control signal interface adapted to receive a first command from the memory controller; an intelligent buffer chip; and emulation and command translation logic adapted to; translate a first address associated with the first command, issue the first command to a first memory device within the plurality of memory devices, determine that the first command is a read command, select a memory data signal interface corresponding to the first memory device, receive a first data burst from the first memory device, delay the first data burst to eliminate a first clock-to-data phase between the one of the first memory device and the interface circuit, and re-drive the first data burst to the memory controller, wherein the plurality of memory devices are arranged in a stack, and the interface circuit is integrated within the stack, and wherein the plurality of the memory devices comprises dynamic random access memories, and the intelligent buffer chip and the dynamic random access memories are included in a dual in-line memory module. - View Dependent Claims (18, 19)
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20. An interface circuit configured to re-time a plurality of data bursts returned by a plurality of memory devices to obtain a contiguous data burst, the interface circuit comprising:
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a system control signal interface adapted to receive a first command from a memory controller; emulation and command translation logic adapted to; translate a first address associated with the first command; issue the first command to a first memory device within the plurality of memory devices corresponding to the first address; determine that the first command is a read command; select a memory data signal interface corresponding to the first memory device; receive a first data burst from the first memory device; delay the first data burst to eliminate a first clock-to-data phase between the first memory device and the interface circuit, and re-drive the first data burst to the memory controller; and
initialization and configuration logic,wherein the system control signal interface is further adapted to receive a second command from the memory controller, and the emulation and command translation logic is further adapted to; translate a second address associated with the second command, issue the second command to a second memory device within the plurality of memory devices corresponding to the second address, determine that the second command is a read command, select a memory data signal interface corresponding to the second memory device, receive a second data burst from the second memory device, delay the second data burst to eliminate a second clock-to-data phase between the second memory device and the interface circuit, and re-drive the second data burst to the memory controller so that the first data burst and the second data burst are combined into a third data burst that is contiguous; wherein the system control signal interface is further adapted to receive a third command from the memory controller, and the emulation and command translation logic is further adapted to; translate a third address associated with the third command, issue the third command to a third memory device within the plurality of memory devices corresponding to the third address, determine that the third command is a write command, select a memory data signal interface corresponding to the third memory device, receive a third data burst from the memory controller; and the memory data signal interface corresponding to the third memory device is adapted to; delay the third data burst to eliminate a third clock-to-data phase between the third memory device and the interface circuit, and re-drive the third data burst to the third memory device; wherein the system control signal interface is further adapted to receive a fourth command from the memory controller, and the emulation and command translation logic is further adapted to determine that the fourth command is a calibration command; and the initialization and calibration logic is adapted to; perform calibration sequence to determine the first, second, and third clock-to- data phases, based on the first clock-to-data phase, set a first delay adjustment within the memory data signal interface corresponding to the first memory device, based on the second clock-to-data phase, set a second delay adjustment within the memory data signal interface corresponding to the second memory device, and based on the third clock-to-data phase, set a third delay adjustment within the memory data signal interface corresponding to the third memory device. - View Dependent Claims (21)
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Specification