Authentication of integrated circuits

• US 8,386,801 B2
• Filed: 03/03/2011
• Issued: 02/26/2013
• Est. Priority Date: 04/16/2002
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Devadas, Srinivas, Gassend, Blaise
• Primary Examiner(s): Flynn, Nathan
• Assistant Examiner(s): AVERY, JEREMIAH L
• Application Number:
  US13/039,391
• Publication Number:
  US 20120033810A1
• Time in Patent Office: 726 Days
• Field of Search: None
• US Class Current: 713/189
• CPC Class Codes: G06F 21/31 User authentication
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/77 in smart cards
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 21/86 Secure or tamper-resistant housings
• CPC Class Codes: G06F 2221/2103 Challenge-response
• CPC Class Codes: G06F 2221/2121 Chip on media, e.g. a disk or tape with a chip embedded in its case
• CPC Class Codes: G06F 2221/2129 Authenticate client device independently of the user
• CPC Class Codes: G06F 2221/2153 Using hardware token as a secondary aspect
• CPC Class Codes: G06Q 20/3674 involving authentication
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/576 using active circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04L 2209/34 Encoding or coding, e.g. Huffman coding or error correction
• CPC Class Codes: H04L 2209/42 : Anonymization, e.g. involving pseudonyms
• CPC Class Codes: H04L 9/0897 : involving additional devices, e.g. trusted platform module [TPM], smartcard or USB
• CPC Class Codes: H04L 9/3278 : using physically unclonable functions [PUF]

Abstract

A group of devices are fabricated based on a common design, each device having a corresponding plurality of measurable characteristics that is unique in the group to that device, each device having a measurement module for measuring the measurable characteristics. Authentication of one of the group of devices is enabled by selective measurement of one or more of the plurality of measurable characteristics of the device.

Claims

1. An integrated circuit device comprising circuitry for repeated generation of a cryptographic key that depends on fabrication characteristics of the integrated circuit and a multiple bit challenge value, said circuitry comprising:

oscillation circuitry comprising a plurality of oscillators for providing a plurality of oscillatory signals, oscillation frequencies of the oscillatory signals being dependent on fabrication characteristics of the oscillation circuitry and on the multiple bit challenge value;

combination circuitry for processing the oscillatory signals and producing outputs each dependent on multiple of the plurality of oscillatory signals; and

a key generator for assembling the cryptographic key to depend on the outputs of the combination circuitry.

2. The device of claim 1 further comprising:

an error mitigation component for processing the outputs of the combination circuitry prior to assembling the cryptographic key.

3. The device of claim 2 wherein the error mitigation component comprises an error correction component.

4. The device of claim 1 wherein the combination circuitry comprises arithmetic combination circuitry for arithmetically combining quantities representing oscillation frequencies of the multiple oscillatory signals.

5. The device of claim 4 wherein the circuitry for arithmetically combining the quantities comprises circuitry for dividing the quantities.

6. The device of claim 1 wherein each oscillator of the plurality of oscillators comprises a plurality comprises a delay loop whose delay depends on fabrication characteristics of the circuitry.

7. The device of claim 6 wherein the delay loop comprises a series of logic gates.

8. The device of claim 6 wherein the delay of the delay loop is further dependent on the challenge value.

9. The device of claim 1 wherein the oscillation circuitry is configured to provide each oscillatory signal using a different one of the plurality of oscillators.

15. The device of claim 1 wherein the plurality of oscillators is configurable according to the multiple bit challenge value.

10. A method for repeated generation of a cryptographic key that depends on fabrication characteristics of an integrated circuit comprising:

operating a plurality of oscillators to provide a plurality of oscillatory signals, oscillation frequencies of the oscillatory signals being dependent on fabrication characteristics of the oscillation circuitry and on a multiple bit challenge value;

combining quantities representing oscillation frequencies of the oscillatory signals to produce outputs each dependent on multiple of the plurality of oscillatory signals; and

assembling a cryptographic key to depend on the outputs of the combining.

11. The method of claim 10 further comprising mitigating errors in the outputs of the combination circuitry prior to assembling the cryptographic key.

12. The method of claim 10 wherein combining the quantities includes arithmetically combining the quantities.

13. The method of claim 12 wherein arithmetically combining the quantities comprises dividing the quantities.

14. The method of claim 10 further comprising repeating generation of the cyptographic key using the multiple bit challenge value previously used to generate the cryptographic key.