Wake-and-go mechanism with data monitoring

• US 8,386,822 B2
• Filed: 02/01/2008
• Issued: 02/26/2013
• Est. Priority Date: 02/01/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arimilli, Ravi K., Sharma, Satya P., Swanberg, Randal C.
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Brown, Michael J
• Application Number:
  US12/024,540
• Publication Number:
  US 20090199029A1
• Time in Patent Office: 1,852 Days
• Field of Search: 713/300, 713/320, 713/323, 718/104
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 2209/544 Remote
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom, specialized instruction, operating system call, or application programming interface call that indicates that a thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address, expected data value, and comparison type associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, logic associated with the CAM performs a comparison based on the data value being written, expected data value, and comparison type.

Claims

1. A method, in a data processing system, for performing a wake-and-go operation, the method comprising:

detecting a thread that is waiting for an event associated with a target address, wherein the event is based on a value being written to the target address that relates to an expected data value by a comparison type;

writing, by a wake-and-go mechanism, an entry in a wake-and-go storage array, wherein the entry comprises the target address, the expected data value, and the comparison type;

placing the thread in a sleep state;

responsive to an event that modifies a data value at the target address, performing a comparison based on the value being written, the expected value, and the comparison type; and

responsive to the comparison matching, placing the thread in a non-sleep state.

2. The method of claim 1, wherein the event is an asynchronous event caused by a device outside a processor running the thread.

3. The method of claim 1, wherein the wake-and-go storage array is a content addressable memory and an address appearing on an address bus is used to address the content addressable memory.

4. The method of claim 3, wherein responsive to the event that modifies the target address, the content addressable memory returns a storage address at which the target address is stored within the content addressable memory.

5. The method of claim 1, wherein detecting a thread that is waiting for an event associated with a target address comprises:

detecting that the thread executes a specialized processor instruction to update the wake-and-go storage array.

6. The method of claim 1, wherein detecting a thread that is waiting for an event associated with a target address comprises:

detecting that the thread makes a call to an operating system to update the wake-and-go storage array.

7. A data processing system, comprising:

a wake-and-go mechanism; and

a wake-and-go array,

wherein the wake-and-go mechanism is configured to;

detect a thread that is waiting for an event associated with a target address, wherein the event is based on a value being written to the target address that relates to an expected data value by a comparison type;

write an entry in the wake-and-go storage array, wherein the entry comprises the target address, the expected data value, and the comparison type;

place the thread in a sleep state;

responsive to an event that modifies a data value at the target address, performing a comparison based on the value being written, the expected value, and the comparison type; and

responsive to the comparison matching, place the thread in a non-sleep state.

8. The data processing system of claim 7, wherein the event is an asynchronous event caused by a device outside a processor running the thread.

9. The data processing system of claim 7, wherein the wake-and-go storage array is a content addressable memory and an address appearing on an address bus is used to address the content addressable memory.

10. The data processing system of claim 9, wherein responsive to the event that modifies the target address, the content addressable memory returns a storage address at which the target address is stored within the content addressable memory.

11. The data processing system of claim 7, wherein detecting a thread that is waiting for an event associated with a target address comprises:

detecting that the thread executes a specialized processor instruction to update the wake-and-go storage array.

12. The data processing system of claim 7, wherein detecting a thread that is waiting for an event associated with a target address comprises:

detecting that the thread makes a call to an operating system to update the wake-and-go storage array.

13. A computer program product comprising a non-transitory computer storage medium having a computer readable program stored thereon, wherein the computer readable program, when executed on a computing device, causes the computing device to:

detect a thread that is waiting for an event associated with a target address, wherein the event is based on a value being written to the target address that relates to an expected data value by a comparison type;

write, by a wake-and-go mechanism, an entry in a wake-and-go storage array, wherein the entry comprises the target address, the expected data value, and the comparison type;

place the thread in a sleep state;

responsive to an event that modifies a data value at the target address, performing a comparison based on the value being written, the expected value, and the comparison type; and

responsive to the comparison matching, place the thread in a non-sleep state.

14. The computer program product of claim 13, wherein the event is an asynchronous event caused by a device outside a processor running the thread.

15. The computer program product of claim 13, wherein the wake-and-go array is a content addressable memory and wherein responsive to an event that modifies the target address, the content addressable memory returns a storage address at which the target address is stored within the content addressable memory.

16. The computer program product of claim 13, wherein detecting a thread that is waiting for an event associated with a target address comprises:

detecting that the thread executes a specialized processor instruction to update the wake-and-go storage array.

17. The computer program product of claim 13, wherein detecting a thread that is waiting for an event associated with a target address comprises:

detecting that the thread makes a call to an operating system to update the wake-and-go storage array.