Automatic internal trimming calibration method to compensate process variation
First Claim
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1. A method of trimming timing in an integrated circuit, comprising:
- applying an external reference signal to the integrated circuit;
comparing the reference signal to an internal signal generated from within the integrated circuit, whereby a sequence of results of the comparing is stored by associating a first value with a plurality of pulses of the internal signal having a failing edge that occurs before a falling edge of a pulse of the reference signal and by associating a second value with a plurality of pulses of the internal signal having a falling edge that occurs after a falling edge of a pulse of the reference signal; and
performing automatic trimming to adjust the internal signal according to a result of the comparing.
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Abstract
A method is described for performing an automatic internal trimming operation that can compensate process variation and supply voltage variation in an integrated circuit. A reference signal is applied when the integrated circuit is in an automatic internal trimming mode, and integrated circuit timing is trimmed into a predetermined target range after applying predefined reference cycles.
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Citations
13 Claims
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1. A method of trimming timing in an integrated circuit, comprising:
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applying an external reference signal to the integrated circuit; comparing the reference signal to an internal signal generated from within the integrated circuit, whereby a sequence of results of the comparing is stored by associating a first value with a plurality of pulses of the internal signal having a failing edge that occurs before a falling edge of a pulse of the reference signal and by associating a second value with a plurality of pulses of the internal signal having a falling edge that occurs after a falling edge of a pulse of the reference signal; and performing automatic trimming to adjust the internal signal according to a result of the comparing. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of trimming timing in an integrated circuit, comprising:
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applying a reference (WE) signal to the integrated circuit, wherein the applying comprises applying a sequence of pulses, each pulse in the sequence having a duty cycle greater than the duty cycle of the previous pulse; generating (a) an internal reference (TGRW) signal, (b) an internal chip control (TGRC) signal, and (c) an internal timing-circuit-generated (SARD) signal; comparing the reference signal with an internal signal generated from the integrated circuit, the comparing including performing sampling according to the SARD signal to produce a sample WEn and further including incrementing n and repeating the sampling until n is greater than a maximum value N, a sequence of results of the sampling being stored by associating a first value with a plurality of pulses of the internal signal having a failing edge that occurs before a falling edge of a pulse of the reference signal and by associating a second value with a plurality of pulses of the internal signal having a falling edge that occurs after a falling edge of a pulse of the reference signal, whereby a pattern of results from the comparing is characterized as too fast, too slow, or on target; and performing automatic trimming to adjust the internal signal according to a result of the comparing. - View Dependent Claims (9, 10, 11)
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12. A method of trimming timing in an integrated circuit, comprising:
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applying a reference signal to the integrated circuit, wherein the applying comprises applying a sequence of pulses, each pulse in the sequence having a duty cycle greater than the duty cycle of the previous pulse; comparing the reference signal to an internal signal generated from the integrated circuit by sampling the reference signal N times according to an internal timing signal, whereby a sequence of results of the sampling being stored by associating a first value with a plurality of pulses of the internal signal having a falling edge that occurs before a falling edge of a pulse of the reference signal and by associating a second value with a plurality of pulses of the internal signal having a falling edge that occurs after a falling edge of a pulse of the reference signal, whereby timing in the integrated circuit is classified by assigning a first classification to timing in the integrated circuit when the sequence of results exhibits a first type of pattern, by assigning a second classification to timing in the integrated circuit when the sequence of results exhibits a second type of pattern, and by assigning a third classification to timing in the integrated circuit when the sequence of results exhibits a third type of pattern, and wherein the comparing comprises interpreting whether a pattern from the comparing corresponds to an “
on target”
criteria;performing automatic trimming to adjust the internal signal according to a result of the comparing; and storing a resulting configuration of the integrated circuit. - View Dependent Claims (13)
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Specification