Automatic internal trimming calibration method to compensate process variation

• US 8,386,829 B2
• Filed: 06/17/2009
• Issued: 02/26/2013
• Est. Priority Date: 06/17/2009
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Hu, Chih-Ting, Hung, Chun-Hsiung, Chen, Ken-Hui
• Primary Examiner(s): Zaman, Faisal M
• Application Number:
  US12/486,573
• Publication Number:
  US 20100321101A1
• Time in Patent Office: 1,350 Days
• Field of Search: 713/503
• US Class Current: 713/503
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

A method is described for performing an automatic internal trimming operation that can compensate process variation and supply voltage variation in an integrated circuit. A reference signal is applied when the integrated circuit is in an automatic internal trimming mode, and integrated circuit timing is trimmed into a predetermined target range after applying predefined reference cycles.

Claims

1. A method of trimming timing in an integrated circuit, comprising:

applying an external reference signal to the integrated circuit;

comparing the reference signal to an internal signal generated from within the integrated circuit, whereby a sequence of results of the comparing is stored by associating a first value with a plurality of pulses of the internal signal having a failing edge that occurs before a falling edge of a pulse of the reference signal and by associating a second value with a plurality of pulses of the internal signal having a falling edge that occurs after a falling edge of a pulse of the reference signal; and

performing automatic trimming to adjust the internal signal according to a result of the comparing.

2. The method as set forth in claim 1, wherein the performing of automatic trimming comprises adjusting at least one internal parameter of the integrated circuit.

3. The method as set forth in claim 1, wherein the adjusting of the internal signal comprises blowing internal fuses, thereby changing a configuration of resistors in order to change a resistance value that controls a frequency of a clock signal.

4. The method as set forth in claim 1, wherein the adjusting of the internal signal comprises blowing internal fuses, thereby changing a configuration of resistors in order to change a resistance value that controls an internal power supply voltage.

5. The method as set forth in claim 1, wherein:

the automatic trimming is performed after the applying of the reference signal; and

an integrated circuit configuration is stored according to a result of the automatic trimming.

6. The method as set forth in claim 1, further comprising passing an integrated circuit according to a result of the comparing.

7. The method as set forth in claim 1, further comprising rejecting an integrated circuit according to a result of the comparing.

8. A method of trimming timing in an integrated circuit, comprising:

applying a reference (WE) signal to the integrated circuit, wherein the applying comprises applying a sequence of pulses, each pulse in the sequence having a duty cycle greater than the duty cycle of the previous pulse;

generating (a) an internal reference (TGRW) signal, (b) an internal chip control (TGRC) signal, and (c) an internal timing-circuit-generated (SARD) signal;

comparing the reference signal with an internal signal generated from the integrated circuit, the comparing including performing sampling according to the SARD signal to produce a sample WE_n and further including incrementing n and repeating the sampling until n is greater than a maximum value N, a sequence of results of the sampling being stored by associating a first value with a plurality of pulses of the internal signal having a failing edge that occurs before a falling edge of a pulse of the reference signal and by associating a second value with a plurality of pulses of the internal signal having a falling edge that occurs after a falling edge of a pulse of the reference signal, whereby a pattern of results from the comparing is characterized as too fast, too slow, or on target; and

performing automatic trimming to adjust the internal signal according to a result of the comparing.

9. The method as set forth in claim 8, in which the generating is performed according to the WE signal.

10. The method as set forth in claim 9, wherein the TGRW signal is derived from the WE signal, the TGRC signal is used to synchronize a plurality of internal reference signals, and the SARD signal is generated by an internal timing circuit based upon the TGRC signal and taking into account fuse information relating to a status of internal trimming in the integrated circuit.

11. The method as set forth in claim 8, wherein the TGRW signal is derived from the WE signal, the TGRC signal is used to synchronize a plurality of internal reference signals, and the SARD signal is generated by an internal timing circuit based upon the TGRC signal and taking into account fuse information relating to a status of internal trimming in the integrated circuit.

12. A method of trimming timing in an integrated circuit, comprising:

applying a reference signal to the integrated circuit, wherein the applying comprises applying a sequence of pulses, each pulse in the sequence having a duty cycle greater than the duty cycle of the previous pulse;

comparing the reference signal to an internal signal generated from the integrated circuit by sampling the reference signal N times according to an internal timing signal, whereby a sequence of results of the sampling being stored by associating a first value with a plurality of pulses of the internal signal having a falling edge that occurs before a falling edge of a pulse of the reference signal and by associating a second value with a plurality of pulses of the internal signal having a falling edge that occurs after a falling edge of a pulse of the reference signal, whereby timing in the integrated circuit is classified by assigning a first classification to timing in the integrated circuit when the sequence of results exhibits a first type of pattern, by assigning a second classification to timing in the integrated circuit when the sequence of results exhibits a second type of pattern, and by assigning a third classification to timing in the integrated circuit when the sequence of results exhibits a third type of pattern, and wherein the comparing comprises interpreting whether a pattern from the comparing corresponds to an “

on target”

criteria;

performing automatic trimming to adjust the internal signal according to a result of the comparing; and

storing a resulting configuration of the integrated circuit.

13. The method as set forth in claim 12, wherein the resulting configuration of the integrated circuit is stored in a fuse information block.