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Memory systems and memory modules

  • US 8,386,833 B2
  • Filed: 10/24/2011
  • Issued: 02/26/2013
  • Est. Priority Date: 06/24/2005
  • Status: Active Grant
First Claim
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1. A memory module, comprising:

  • at least one memory chip; and

    a first intelligent chip coupled to the at least one memory chip and adapted to be coupled to a memory controller, wherein the intelligent chip is configured to implement at least a part of a reliability and serviceability (RAS) feature; and

    a second intelligent chip coupled to the at least one memory chip and adapted to be coupled to the memory controller, and a sideband bus that couples the intelligent chip to the second intelligent chip,wherein information is communicated over the sideband bus to prompt either the intelligent chip or second intelligent chip to substitute data from good memory bits in the at least one memory chip for data from known bad memory bits in the at least one memory chip using a lookaside buffer.

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