Memory systems and memory modules

• US 8,386,833 B2
• Filed: 10/24/2011
• Issued: 02/26/2013
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Smith, Michael J. S., Rajan, Suresh Natarajan
• Primary Examiner(s): PATEL, KAMINI B
• Application Number:
  US13/280,251
• Publication Number:
  US 20120042204A1
• Time in Patent Office: 491 Days
• Field of Search: 714/5.1
• US Class Current: 714/5.1
• CPC Class Codes: G01K 13/00 Thermometers specially adapted for specific purposes
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 15/7821 Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
• CPC Class Codes: G06F 17/00 Digital computing or data processing equipment or methods, specially adapted for specific functions information retrieval, database structures or file system structures therefor G06F16/00
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

Claims

1. A memory module, comprising:

at least one memory chip; and

a first intelligent chip coupled to the at least one memory chip and adapted to be coupled to a memory controller, wherein the intelligent chip is configured to implement at least a part of a reliability and serviceability (RAS) feature; and

a second intelligent chip coupled to the at least one memory chip and adapted to be coupled to the memory controller, and a sideband bus that couples the intelligent chip to the second intelligent chip,

wherein information is communicated over the sideband bus to prompt either the intelligent chip or second intelligent chip to substitute data from good memory bits in the at least one memory chip for data from known bad memory bits in the at least one memory chip using a lookaside buffer.

2. The memory module of claim 1, wherein the first intelligent chip is configured to control a light-emitting diode to indicate a failure of the memory module.

3. The memory module of claim 1, wherein the RAS feature comprises a self-test performed on the memory module.

4. The memory module of claim 3, wherein the intelligent chip is configured to control one or more light-emitting diodes to indicate a failed or successful self-test.

5. The memory module of claim 1, wherein the RAS feature comprises memory sparing.

6. The memory module of claim 5, wherein the intelligent chip is configured to calculate replacement possibilities, optimize a replacement based on a replacement strategy, notify the host system of memory sparing operations being performed, and perform a memory sparing substitution or replacement.

7. The memory module of claim 1, wherein the first intelligent chip transmits a signal to the intelligent buffer chip to turn off an output buffer associated with the intelligent buffer chip.

8. The memory module of claim 1, wherein control information is communicated over the sideband bus that includes an indication of a data flow direction, at least one port identifier, and an indication of a number of byte lanes per port.

9. The memory module of claim 1, wherein control information is communicated over the sideband bus in the form of a fixed-format command packet.