On-chip non-volatile storage of a test-time profile for efficiency and performance control

• US 8,386,859 B2
• Filed: 04/30/2010
• Issued: 02/26/2013
• Est. Priority Date: 04/30/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Kursun, Eren, Emma, Philip G., Gates, Stephen M.
• Primary Examiner(s): Merant, Guerrier
• Application Number:
  US12/771,387
• Publication Number:
  US 20110271161A1
• Time in Patent Office: 1,033 Days
• Field of Search: None
• US Class Current: 714/718
• CPC Class Codes: G06F 11/24 Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3062 where the monitored property is the power consumption power management in a computing system G06F1/3203
• CPC Class Codes: G06F 11/3089 Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents software debugging using additional hardware using a specific debug interface G06F11/3656; performance evaluation by tracing or monitoring G06F11/3466

Abstract

Mechanisms for controlling an operation of one or more cores on an integrated circuit chip are provided. The mechanisms retrieve, from an on-chip non-volatile memory of the integrated circuit chip, baseline chip characteristics data representing operational characteristics of the one or more cores prior to the integrated circuit chip being operational in the data processing system. Current operational characteristics data of the one or more cores are compared with the baseline chip characteristics data. Deviations of the current operational characteristics data from the baseline chip characteristics data are determined and used to determine modifications to an operation of the one or more cores. Control signals are sent to one or more on-chip management units based on the determined modifications to cause the operation of the one or more cores to be modified.

Claims

1. A method, in a data processing system, for controlling an operation of one or more on-chip hardware devices on an integrated circuit chip, comprising:

retrieving, from an on-chip non-volatile memory of the integrated circuit chip, baseline chip characteristics data representing operational characteristics of the one or more on-chip hardware devices prior to the integrated circuit chip being operational in the data processing system;

comparing current operational characteristics data of the one or more on-chip hardware devices on the integrated circuit chip with the baseline chip characteristics data;

determining deviations of the current operational characteristics data of the one or more on-chip hardware devices on the integrated circuit chip from the baseline chip characteristics data;

determining modifications to an operation of the one or more on-chip hardware devices based on the determined deviations; and

sending control signals to one or more on-chip management units to cause the operation of the one or more on-chip hardware devices to be modified in accordance with the determined modifications.

2. The method of claim 1, wherein the baseline chip characterization data is generated from manufacturer test data collected by an off-chip tester device after fabrication of the integrated circuit chip but prior to the chip being operational in the data processing system.

3. The method of claim 1, further comprising:

updating the baseline chip characteristics map data during operation of the integrated circuit chip in the data processing system, based on the current operational characteristics data, to generate an updated chip characteristics data structure; and

storing the updated chip characteristics data structure in the on-chip non-volatile memory.

4. The method of claim 1, wherein the current operational characteristics data is gathered from outputs from at least one of on-chip sensors or on-chip hardware counters that measure a performance of the one or more on-chip hardware devices on the integrated circuit chip.

5. The method of claim 1, wherein determining deviations of the current operational characteristics data from the baseline chip characteristics data comprises determining if an on-chip hardware device, in the one or more on-chip hardware devices, on the integrated circuit chip is suffering from performance degradation of the operation of the on-chip hardware device, and wherein determining modifications to an operation of the one or more on-chip hardware devices based on the determined deviations comprises modifying the operation to reduce a stress applied to the on-chip hardware device if it is determined that the on-chip hardware device is suffering from performance degradation of the operation of the on-chip hardware device.

6. The method of claim 1, wherein the modifications to the operation of the one or more on-chip hardware devices comprises at least one of modifying an operating frequency of the one or more on-chip hardware devices, disabling a on-chip hardware device in the one or more on-chip hardware devices, modifying a voltage supply of the one or more on-chip hardware devices, or adjusting a workload executed on the one or more on-chip hardware devices.

7. The method of claim 1, wherein the method is implemented by on-chip logic of the integrated circuit chip provided in an on-chip characterization device of the integrated circuit chip.

8. The method of claim 7, wherein the baseline chip characteristics data is generated from an off-chip tester device performing at least one of wafer or module level tests on the integrated circuit chip, and wherein the off-chip tester device provides the baseline chip characteristic data to the on-chip characterization device.

9. The method of claim 8, wherein the at least one of wafer or module level tests comprise at least one of functional tests of functional units in the one or more on-chip hardware devices, corner tests, burn-in tests, or on-chip sensor calibration processes.

10. The method of claim 1, wherein the baseline operational characteristics data comprises at least one of a voltage range, a frequency range, a power consumption, and a temperature.

11. The method of claim 3, wherein the on-chip non-volatile memory comprises a first portion for permanently storing the baseline chip characteristics data and a second portion for storing the updated chip characteristics data structure in a rewritable manner.

12. The method of claim 11, wherein the first portion comprises at least one bank of fuses, a floating gate programmable memory (PROM), a magneto-resistive memory, an oxide based resistive memory, a bank of anti-fuses, or a phase change memory.

13. An integrated circuit chip, comprising:

one or more on-chip hardware devices;

an on-chip characterization device coupled to the one or more on-chip hardware devices;

an on-chip non-volatile memory coupled to the on-chip characterization device; and

one or more on-chip management units coupled to the one or more on-chip hardware devices and the on-chip characterization device, wherein the on-chip characterization device comprises logic configured to;

retrieve, from the on-chip non-volatile memory, baseline chip characteristics data representing operational characteristics of the one or more on-chip hardware devices prior to the integrated circuit chip being operational in a data processing system;

compare current operational characteristics data of the one or more on-chip hardware devices on the integrated circuit chip with the baseline chip characteristics data;

determine deviations of the current operational characteristics data of the one or more on-chip hardware devices on the integrated circuit chip from the baseline chip characteristics data;

determine modifications to an operation of the one or more on-chip hardware devices based on the determined deviations; and

send control signals to one or more on-chip management units to cause the operation of the one or more on-chip hardware devices to be modified in accordance with the determined modifications.

14. The integrated circuit chip of claim 13, wherein the baseline chip characterization data is generated from manufacturer test data collected by an off-chip tester device after fabrication of the integrated circuit chip but prior to the chip being operational in a data processing system, and wherein the baseline chip characterization data is provided by the off-chip tester device to the on-chip characterization device.

15. The integrated circuit chip of claim 13, wherein the on-chip characterization device further comprises logic configured to:

update the baseline chip characteristics data during operation of the integrated circuit chip in the data processing system, based on the current operational characteristics data, to generate an updated chip characteristics data structure; and

store the updated chip characteristics data structure in the on-chip non-volatile memory.

16. The integrated circuit chip of claim 13, wherein the current operational characteristics data is gathered from outputs from at least one of on-chip sensors or on-chip hardware counters provided on the integrated circuit chip that measure a performance of the one or more on-chip hardware devices.

17. The integrated circuit chip of claim 13, wherein logic of the on-chip characterization device is further configured to determine deviations of the current operational characteristics data from the baseline chip characteristics data by determining if a on-chip hardware device, in the one or more on-chip hardware devices, on the integrated circuit chip is suffering from performance degradation of the operation of the on-chip hardware device, and determine modifications to an operation of the one or more on-chip hardware devices based on the determined deviations by modifying the operation to reduce a stress applied to the on-chip hardware device if it is determined that the on-chip hardware device is suffering from performance degradation of the operation of the on-chip hardware device.

18. The integrated circuit chip of claim 13, wherein the modifications to the operation of the one or more on-chip hardware devices comprises at least one of modifying an operating frequency of the one or more on-chip hardware devices, disabling a on-chip hardware device in the one or more on-chip hardware devices, modifying a voltage supply of the one or more on-chip hardware devices, or adjusting a workload executed on the one or more on-chip hardware devices.

19. The integrated circuit chip of claim 15, wherein the on-chip non-volatile memory comprises a first portion for permanently storing the baseline chip characteristics data and a second portion for storing the updated chip characteristics data structure in a rewritable manner.

20. The integrated circuit chip of claim 13, wherein the first portion comprises at least one bank of fuses, a floating gate programmable memory (PROM), a magneto-resistive memory, an oxide based resistive memory, a bank of anti-fuses, or a phase change memory.