Strain bars in stressed layers of MOS devices

• US 8,389,316 B2
• Filed: 04/19/2011
• Issued: 03/05/2013
• Est. Priority Date: 03/13/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Yen-Sen, Lin, Chung-Te, Cao, Min, Yang, Sheng-Jier
• Primary Examiner(s): TRAN, LONG K
• Application Number:
  US13/089,765
• Publication Number:
  US 20110195554A1
• Time in Patent Office: 686 Days
• Field of Search: 438/50, 438/197, 438/128, 438/129, 438/189, 438/309
• US Class Current: 438/50
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.

Claims

1. A method of forming a semiconductor structure, the method comprising:

forming an isolation region in a semiconductor substrate, wherein the isolation region adjoins an active region in the semiconductor substrate;

forming a metal-oxide-semiconductor (MOS) device comprising;

forming a gate electrode over the active region; and

forming a source region and a drain on opposing sides of the gate electrode;

forming a stressor layer over the active region and the isolation region; and

forming a strain bar overlaying the isolation region, wherein the strain bar is encircled by the stressor layer, wherein the steps of forming the stressor layer and the strain bar comprise;

blanket forming a dummy stressor layer having an opposite stress type than the stressor layer;

etching the dummy stressor layer to leave the strain bar;

forming the stressor layer over the strain bar and the MOS device; and

etching a portion of the stressor layer directly over the strain bar.

2. A method of forming a semiconductor structure, the method comprising:

providing a semiconductor substrate comprising an active region therein;

providing an isolation region in the semiconductor substrate and adjoining the active region;

forming a metal-oxide-semiconductor (MOS) device comprising;

forming a gate electrode over the active region; and

forming a source region and a drain region on opposing sides of the gate electrode;

forming a stressor layer over the active region and the isolation region; and

forming a strain bar overlying the isolation region, wherein the strain bar is encircled by the stressor layer, and wherein the step of forming the strain bar comprises;

forming an opening in the stressor layer and overlying the isolation region; and

filling the opening to form the strain bar.

3. The method of claim 2, wherein the strain bar is in a path of a detrimental stress applied to the MOS device by the stressor layer, and wherein the stressor layer is free from strain bars therein in paths of beneficial stresses applied to the MOS device by the stressor layer.

4. The method of claim 2 further comprising:

forming an inter-layer dielectric (ILD) over the stressor layer after the step of forming the opening, wherein the step of filling the opening comprises filling a portion of the ILD into the opening; and

forming a contact plug in the ILD and electrically connected to one of the source and drain regions.

5. The method of claim 2 further comprising:

forming an ILD over the stressor layer, wherein the step of forming the opening is performed after the step of forming the ILD;

forming a contact plug in the ILD and electrically connected to one of the source and drain regions; and

forming a dummy contact plug in the ILD, wherein the step of filling the opening comprises forming a portion of the dummy contact plug in the opening.

6. The method of claim 2, wherein the strain bar and a nearest boundary of the source and drain regions have a distance of less than about 0.3 μ

m.

7. A method of forming a semiconductor structure, the method comprising:

providing a semiconductor substrate comprising an active region therein;

providing a shallow trench isolation (STI) region in the semiconductor substrate and adjoining the active region;

forming a metal-oxide-semiconductor (MOS) device comprising;

forming a gate electrode over the active region; and

forming a source region and a drain region on opposing sides of the gate electrode;

forming a contact etch stop layer (CESL) over the active region and the STI region;

forming an opening in the CESL and directly overlying the STI region; and

filling the opening to form a strain bar.

8. The method of claim 7, wherein the strain bar is in a path of a detrimental inherent stress applied by the CESL, and wherein the CESL is free from strain bars therein in paths of beneficial stresses applied by the CESL.

9. The method of claim 7 further comprising:

forming an inter-layer dielectric (ILD) over the CESL after the step of forming the opening, wherein the step of filling the opening comprises filling a portion of the ILD into the opening; and

forming a contact plug in the ILD and electrically connected to one of the source and drain regions.

10. The method of claim 7 further comprising:

forming an ILD over the CESL, wherein the step of forming the opening is performed after the step of forming the ILD;

forming a contact plug in the ILD; and

forming a dummy plug contact plug in the ILD, wherein the step of filling the opening comprises forming a portion of the dummy plug in the opening.

11. The method of claim 7, wherein the strain bar and a nearest boundary of the source and drain regions has a distance of less than about 0.3 μ

m.