Semiconductor device and manufacturing method thereof

• US 8,389,417 B2
• Filed: 11/12/2010
• Issued: 03/05/2013
• Est. Priority Date: 11/13/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun
• Primary Examiner(s): Nhu, David
• Application Number:
  US12/945,516
• Publication Number:
  US 20110114945A1
• Time in Patent Office: 844 Days
• Field of Search: 438/722, 438/706, 438/745, 438/692, 438/680, 438/663, 438/513, 438/475, 438/474, 438/392, 438/240, 438/241, 438/197, 257/56, 257/192, 257/213, 257/288, 257/E21.006, 257/E21.051, 257/E21.077, 257/E21.17, 257/E21.2, 257/E21.23, 257/E21.227, 257/E21.229, 257/E21.304, 257/E21.311, 257/E21.32, 257/E21.37
• US Class Current: 438/722
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00

Abstract

An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode. The second source electrode and the second drain electrode include an oxide region formed by oxidizing a side surface thereof, and at least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode.

Claims

1. A semiconductor device comprising:

a first transistor including;

impurity regions provided in a substrate including a semiconductor material;

a channel formation region between the impurity regions;

a first gate insulating layer over the channel formation region;

a first gate electrode over the first gate insulating layer; and

a first source electrode and a first drain electrode electrically connected to the impurity regions; and

a second transistor including;

an oxide semiconductor layer over the substrate including the semiconductor material;

a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer;

a second gate insulating layer covering the oxide semiconductor layer, the second source electrode, and the second drain electrode; and

a second gate electrode over the second gate insulating layer,

wherein the second source electrode and the second drain electrode include an oxide region at a side surface of the second source electrode and the second drain electrode, and

wherein at least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode.

2. The semiconductor device according to claim 1, wherein the oxide region of the second source electrode and the second drain electrode is formed by a plasma treatment with a frequency power of 300 MHz to 300 GHz, and by using a mixed gas of oxygen and argon.

3. The semiconductor device according to claim 1, further comprising a protective insulating layer over the second source electrode and the second drain electrode, wherein the protective insulating layer has a substantially same planar shape as a planar shape of the second source electrode and the second drain electrode.

4. The semiconductor device according to claim 1, wherein a hydrogen concentration of the oxide semiconductor layer is 5×

10¹⁹/cm³ or less.

5. The semiconductor device according to claim 1, wherein an off-state current of the second transistor is 1×

10<sup>−

13</sup> A or less.

6. The semiconductor device according to claim 1, wherein the substrate including the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

7. The semiconductor device according to claim 1, wherein the semiconductor material is silicon.

8. The semiconductor device according to claim 1, wherein the semiconductor device is incorporated in one selected from the group consisting of a computer, a personal digital assistant, an electronic book, a phone, a camera, and a television set.

9. A manufacturing method of a semiconductor device, comprising:

forming a first transistor, the steps of forming the first transistor comprising;

forming a gate insulating layer over a substrate including a semiconductor material;

forming a gate electrode over the gate insulating layer;

forming a channel formation region and impurity regions by adding an impurity element to the substrate including the semiconductor material; and

forming a first source electrode and a first drain electrode electrically connected to the impurity regions; and

forming a second transistor, the steps of forming the second transistor comprising;

forming an oxide semiconductor layer over the first transistor;

forming a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer;

oxidizing a side surface of the second source electrode and the second drain electrode;

forming a second gate insulating layer covering the oxide semiconductor layer, the second source electrode, and the second drain electrode; and

forming a second gate electrode over the second gate insulating layer.

10. The manufacturing method of a semiconductor device according to claim 9, wherein the side surface of the second source electrode and the second drain electrode is oxidized by a plasma treatment with a frequency power of 300 MHz to 300 GHz, and by using a mixed gas of oxygen and argon.

11. The manufacturing method of a semiconductor device according to claim 9, wherein at least one of the second gate electrode, the second source electrode, and the second drain electrode is formed so as to be electrically connected to at least one of the first gate electrode, the first source electrode, and the first drain electrode.

12. The manufacturing method of a semiconductor device according to claim 9, further comprising the step of forming a protective insulating layer having a substantially same planar shape as a planar shape of the second source electrode and the second drain electrode over the second source electrode and the second drain electrode.

13. The manufacturing method of a semiconductor device according to claim 9, wherein an off-state current of the second transistor is made 1×

10<sup>−

13</sup> A or less by making a hydrogen concentration of the oxide semiconductor layer 5×

10¹⁹/cm³ or less.

14. The manufacturing method of a semiconductor device according to claim 9, wherein a single crystal semiconductor substrate or an SOI substrate is used as the substrate including the semiconductor material.

15. The manufacturing method of a semiconductor device according to claim 9, wherein the semiconductor material is silicon.

16. The manufacturing method of a semiconductor device according to claim 9, wherein the semiconductor device is incorporated in one selected from the group consisting of a computer, a personal digital assistant, an electronic book, a phone, a camera, and a television set.