Power semiconductor devices, structures, and related methods

• US 8,390,060 B2
• Filed: 07/05/2011
• Issued: 03/05/2013
• Est. Priority Date: 07/06/2010
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Zeng, Jun, Blachard, Richard A.
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): SYLVIA, CHRISTINA A
• Application Number:
  US13/175,975
• Publication Number:
  US 20120098055A1
• Time in Patent Office: 609 Days
• Field of Search: 438/42, 438/108, 438/142, 257/46, 257/79, 257/330, 257/331, 257/334, 257/341, 977/700
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0873 Drain regions
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.

Claims

1. A semiconductor device, comprising:

a first-conductivity-type semiconductor source region;

a second-conductivity-type semiconductor body region;

a gate electrode, which is capacitively coupled to invert a portion of said body region, to thereby create a channel;

a semiconductor drift region which includes both first-conductivity-type and second-conductivity-type semiconductor portions in parallel;

immobile electrostatic charge which is capacitively coupled to invert parts of said second-conductivity-type drift region portions; and

a first-conductivity-type semiconductor drain region;

wherein said body region is interposed between said source region and said drift region;

and wherein said drift region is interposed between said body region and said drain region;

and further comprising an intermediate layer which has a first conductivity type, and has a higher doping than said first-conductivity-type semiconductor portion, and which electrically connects said channel both laterally and vertically to both said first-conductivity-type and said second-conductivity-type semiconductor portions, and which is physically interposed between said channel and both said first-conductivity-type and said second-conductivity-type semiconductor portions;

whereby, in the ON state, majority carriers flow both through said first-conductivity-type portions, and at least some parts of said second-conductivity-type portions of said drift region, in parallel.

2. The device of claim 1, wherein said first-conductivity-type source region is n-type, and said majority carriers are electrons.

3. The device of claim 1, wherein said source, body, intermediate, and drain regions are silicon.

4. The device of claim 1, wherein said immobile electrostatic charge is provided by cesium ions.

5. The device of claim 1, wherein said immobile electrostatic charge consists of point charges.

6. The device of claim 1, wherein said immobile electrostatic charge is provided by ions in dielectric material and/or by ions at a dielectric/semiconductor interface.

7. The device of claim 1, wherein said gate electrode lies entirely inside a trench.

8. The device of claim 1, wherein said immobile electrostatic charge is provided by ions in dielectric material in a trench.

9. The device of claim 8, wherein said trench includes a void.

10. A semiconductor device, comprising:

an n-type semiconductor source region;

a p-type semiconductor body region;

a gate electrode, which is capacitively coupled to invert a portion of said body region, to thereby create a channel;

a semiconductor drift region which includes both n-type and p-type semiconductor portions electrically connected in parallel;

immobile positive ions which are capacitively coupled to jointly invert parts of said p-type drift region portions; and

an n-type semiconductor drain region;

wherein said body region is interposed between said source region and said drift region;

and wherein said drift region is interposed between said body region and said drain region;

and further comprising an n-type intermediate layer which has a higher doping than said n-type semiconductor portion of said drift region, and which electrically connects said channel both laterally and vertically to both said n-type and said p-type semiconductor portions, and which is physically interposed between said channel and both said n-type and said p-type semiconductor portions;

whereby, in the ON state, electrons flow both through said n-type portions and said p-type portions of said drift region in parallel.

11. The device of claim 10, wherein said source, body, drain and drift regions are silicon.

12. The device of claim 10, wherein said immobile positive ions are cesium ions.

13. The device of claim 10, wherein said gate electrode lies entirely inside a trench.

14. A semiconductor device, comprising:

a first-conductivity-type semiconductor source region;

a second-conductivity-type semiconductor body region;

a gate electrode, which is capacitively coupled to invert a portion of said body region, to thereby create a channel;

a semiconductor drift region which includes both first-conductivity-type and second-conductivity-type semiconductor portions in parallel;

immobile electrostatic charge which is capacitively coupled to invert parts of said second-conductivity-type drift region portions; and

a first-conductivity-type semiconductor drain region;

wherein said body region is interposed between said source region and said drift region;

and wherein said drift region is interposed between said body region and said drain region;

whereby, in the ON state, majority carriers flow both through said first-conductivity-type portions and said second-conductivity-type portions of said drift region in parallel;

wherein said gate electrode lies in a first trench; and

wherein said immobile electrostatic charge lies in one or more second trenches; and

wherein said first trench has a different depth than said one or more second trenches.

15. The device of claim 14, wherein said first-conductivity-type source region is n-type, and said majority carriers are electrons.

16. The device of claim 14, wherein said source, body, drain and drift regions are silicon.

17. The device of claim 14, wherein said immobile electrostatic charge is provided by cesium ions.

18. The device of claim 14, wherein said immobile electrostatic charge consists of point charges.

19. The device of claim 14, wherein said immobile electrostatic charge is provided by ions in dielectric material and/or by ions at a dielectric/semiconductor interface.

20. The device of claim 14, wherein said gate electrode lies entirely inside a trench.

21. The device of claim 14, wherein said immobile electrostatic charge is provided by ions in dielectric material in a trench.

22. The device of claim 21, wherein said trench includes a void.