Semiconductor device and method of manufacturing semiconductor device including wiring via and switch via for connecting first and second wirings

• US 8,390,124 B2
• Filed: 02/16/2010
• Issued: 03/05/2013
• Est. Priority Date: 02/17/2009
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Inoue, Naoya, Hayashi, Yoshihiro, Kaneko, Kishou
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US12/656,728
• Publication Number:
  US 20100207093A1
• Time in Patent Office: 1,113 Days
• Field of Search: 257/107, 257/130, 257/131, 257/155, 257/156, 257/160, 257/161, 257/758, 257/774, 257/E27.052, 257/E27.079, 257/E27.132, 257/E29.029, 257/E29.036, 257/E29.037, 257/E29.038, 257/E29.043, 257/E29.046, 257/E29.047, 257/E29.048, 257/E29.113, 257/E29.123, 257/E29.125, 257/E29.181, 257/E29.197, 257/E29.224, 257/E29.225, 257/E29.337, 257/E45.002, 257/E45.003, 257/E45.004
• US Class Current: 257/758
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H10N 70/028 by conversion of electrode material, e.g. oxidation
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

Claims

1. A semiconductor device, comprising:

a substrate;

a first wiring layer formed over the substrate;

a first wiring formed in the first wiring layer;

a second wiring layer located above the first wiring layer;

a second wiring formed in the second wiring layer;

a wiring via for connecting the first wiring and the second wiring; and

a switch via for connecting the first wiring and the second wiring,

wherein the switch via comprises at a bottom thereof a resistance change layer,

wherein the wiring via and the second wiring comprise a barrier metal,

wherein the wiring via and the second wiring comprises a region which electrically connects the wiring via with the second wiring without the barrier metal, and

wherein the switch via and the second wiring are further electrically connected through the barrier metal.

2. A semiconductor device according to claim 1, wherein the wiring via is formed in a layer in which the switch via is formed.

3. A semiconductor device according to claim 1, wherein the switch via comprises a metal except for the resistance change layer.

4. A semiconductor device according to claim 3, wherein the resistance change layer includes an upper electrode layer located between the metal forming the switch via and the resistance change layer.

5. A semiconductor device according to claim 4, wherein the resistance change layer and the upper electrode layer are formed at the bottom and on a side of the switch via.

6. A semiconductor device according to claim 4, wherein the upper electrode layer includes one of a single layer film comprising one selected from a first group consisting of Ta, Ti, W, Ru, Pt, Ir, a nitride of Ta, a nitride of Ti, a nitride of W, a nitride of Ru, a nitride of Pt, and a nitride of Ir, and a laminated film in which two or more selected from the first group are laminated.

7. A semiconductor device according to claim 1, wherein the resistance change layer is directly connected to the first wiring.

8. A semiconductor device according to claim 1, wherein the switch via comprises a switch element that includes a lower electrode layer located between the first wiring and the resistance change layer.

9. A semiconductor device according to claim 8, wherein the resistance change layer and the lower electrode layer are formed at the bottom and on a side of the switch via.

10. A semiconductor device according to claim 1, wherein the resistance change layer includes a metal oxide layer.

11. A semiconductor device according to claim 10, wherein the resistance change layer includes an oxide of copper.

12. A semiconductor device according to claim 1, wherein the first wiring and the second wiring comprise a metal comprising 95 wt % or more copper.

13. A semiconductor device according to claim 1, wherein the second wiring comprises a dual damascene structure.

14. A semiconductor device according to claim 1, wherein the second wiring layer comprises a wiring layer which is immediately above the first wiring layer.

15. A semiconductor device, comprising:

a substrate;

a first wiring layer formed over the substrate;

a first wiring formed in the first wiring layer;

a second wiring layer located above the first wiring layer;

a second wiring formed in the second wiring layer;

a wiring via for connecting the first wiring and the second wiring; and

a switch via for further connecting the first wiring and the second wiring,

wherein the switch via comprises a resistance change layer,

wherein the switch via comprises a single damascene structure, and

wherein the wiring via comprises a dual damascene structure.

16. A semiconductor device according to claim 15, wherein the switch via and the wiring layer are formed in a same layer.

17. A semiconductor device according to claim 15, wherein the second wiring comprises a barrier metal, and the switch via is directly connected to the barrier metal of the second wiring.

18. A semiconductor device according to claim 15, wherein the switch via and the wiring via have substantially a same height in a sectional view.

19. A semiconductor device according to claim 15, wherein the resistance change layer is formed at a bottom of the switch via.

20. A semiconductor device according the claim 15, wherein the resistance change layer comprises a metal oxide.