Encoding apparatus, information processing apparatus, encoding method, and data transmission method

• US 8,390,482 B2
• Filed: 08/03/2010
• Issued: 03/05/2013
• Est. Priority Date: 08/12/2009
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Fukuda, Kunio
• Primary Examiner(s): WILLIAMS, HOWARD L
• Application Number:
  US12/849,178
• Publication Number:
  US 20110038428A1
• Time in Patent Office: 945 Days
• Field of Search: 341/56, 341/57, 341/58, 341/59, 341/106, 375/292
• US Class Current: 341/56
• CPC Class Codes: H03M 5/20 the pulses having more than three levels
• CPC Class Codes: H04B 14/023 using pulse amplitude modulation
• CPC Class Codes: H04B 3/548 the power on the line being DC arrangements for feeding power H04L12/10; extracting feeding power from signals H04L25/02
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes

Abstract

Provided is an encoding apparatus including an encoding unit that generates encoded data formed from a sequence of base-k data in which m pieces (m<n) of base-k symbols are combined, by converting input binary data in units of n bits based on a specific conversion rule that associates n-bit binary data and the base-k data. In case a DC balance of the base-k data obtained after conversion has a polarity, the encoding unit controls a polarity of a symbol included in the base-k data obtained after conversion such that the polarity of the DC balance of the base-k data obtained after conversion is different from a polarity of a DC balance of a sequence of base-k data previous to the base-k data obtained after conversion.

Claims

1. An encoding apparatus comprising:

an encoding unit that generates encoded data formed from a sequence of base-k data in which m pieces (m<

n) of base-k symbols are combined, by converting input n-bit binary data, in units of n bits, based on a specific conversion rule that associates n-bit binary data and the base-k data,

wherein the specific conversion rule is a conversion rule that associates the n-bit binary data and the base-k data whose DC balance is zero;

wherein a combination of the k, m, and n (k, m, n) is either (4, 5,

     6) or (3, 7,

     8).

2. An information processing apparatus comprising:

a first module that includes;

an encoding unit to generate encoded data by converting input n-bit binary data, in units of n bits, based on a specific conversion rule that associates n-bit binary data and base-k data in which m pieces (m<

n) of base-k symbols are combined, and by controlling, in case a DC balance of the base-k data obtained after conversion has a polarity, a polarity of a symbol included in the base-k data obtained after conversion such that the polarity of the DC balance of the base-k data obtained after conversion is different from a polarity of a DC balance of a sequence of base-k data previous to the base-k data obtained after conversion, and

a data transmitting unit to transmit the encoded data generated by the encoding unit; and

a second module that includes

a data receiving unit to receive the encoded data transmitted from the first module, and

a decoding unit to detect the polarity of the DC balance of each of the base-k data included in the encoded data received by the data receiving unit, and to decode the encoded data based on the polarity of the DC balance of each of the base-k data that has been detected and based on the specific conversion rule;

wherein the first module further includes a clock addition unit to synchronously add, to the encoded data, a clock having an amplitude value larger than a maximum value for the symbol and having a speed half a symbol speed,

wherein the second module further includes a clock regeneration unit to detect a cycle of polarity inversion of an amplitude of the encoded data received by the data receiving unit and to regenerate the clock based on the detection result, and

wherein the decoding unit decodes the encoded data by using the clock regenerated by the clock regeneration unit.

3. The information processing apparatus according to claim 2,

wherein, among the n-bit binary data, K pieces of the n-bit binary data are associated with the base-k data having a DC balance of zero and (2ⁿ−

K) pieces of the n-bit binary data are associated with the base-k data having a positive DC balance, according to the specific conversion rule,

wherein, in case the DC balance of the base-k data obtained after conversion is positive, if a sequence of base-k data previous to the base-k data obtained after conversion has a positive DC balance, the encoding unit reverses signs of m symbols included in the base-k data obtained after conversion, and

wherein the decoding unit decodes the encoded data based on the specific conversion rule after reversing a sign of each symbol included in base-k data for which a negative DC balance is detected.

4. The information processing apparatus according to claim 2,

wherein the first module further includes a storage unit that stores:

a first conversion table to associate K pieces of the n-bit binary data with the base-k data having a DC balance of zero, according to the specific conversion rule,

a second conversion table to associate (2ⁿ−

K) pieces of the n-bit binary data with the base-k data having a positive DC balance, according to the specific conversion rule, and

a third conversion table to associate the (2ⁿ−

K) pieces of the n-bit binary data with base-k data having a negative DC balance, the base-k data having a negative DC balance being obtained by reversing signs of m symbols included in the base-k data having a positive DC balance,

wherein, in case the n-bit binary data that is to be converted corresponds to the (2ⁿ−

K) pieces of the n-bit binary data, if a sequence of base-k data previous to base-k data to be obtained by converting the n-bit binary data that is to be converted has a positive DC balance in a sequence of the base-k data, the encoding unit converts the n-bit binary data that is to be converted by using the third conversion table, and if the sequence of the base-k data previous to the base-k data to be obtained by converting the n-bit binary data that is to be converted has a negative DC balance, the encoding unit converts the n-bit binary data that is to be converted by using the second conversion table,

wherein the second module further includes a storage unit to store the first conversion table, the second conversion table, and the third conversion table, and

wherein the decoding unit decodes the encoded data by using the first conversion table for base-k data for which a DC balance of zero is detected, by using the second conversion table for base-k data for which a positive DC balance is detected, and by using the third conversion table for base-k data for which a negative DC balance is detected.

5. The information processing apparatus according to claim 2,

wherein the first module and the second module are connected by a specific signal line,

wherein the data transmitting unit generates a superimposed signal by superimposing a power signal supplied from a DC power supply on the encoded data, and transmits the superimposed signal through the specific signal line, and

wherein the data receiving unit receives the superimposed signal through the specific signal line, and separates the power signal and the encoded data from the superimposed signal.

6. The information processing apparatus according to claim 2,

wherein the first module further includes an arithmetic processing unit that outputs at least display data,

wherein the second module further includes a display unit that displays the display data,

wherein the encoding unit generates encoded data by converting binary data corresponding to the display data output from the arithmetic processing unit into a sequence of the base-k data, and

wherein the decoding unit restores the binary data corresponding to the display data by decoding the encoded data, and inputs the binary data to the display unit.

7. An information processing apparatus comprising:

a first module that includes

an encoding unit to generate encoded data by converting input n-bit binary data, in units of n bits, based on a specific conversion rule that associates n-bit binary data and base-k data in which m pieces (m<

n) of base-k symbols are combined in such a way that a DC balance becomes zero, and

a data transmitting unit to transmit the encoded data generated by the encoding unit; and

a second module that includes;

a data receiving unit to receive the encoded data transmitted from the first module, and

a decoding unit to decode the encoded data received by the data receiving unit, based on the specific conversion rule;

wherein a combination of the k, m, and n (k, m, n) is either (4, 5,

     6) or (3, 7,

     8).