System and method of analog-to-digital converters

• US 8,390,487 B2
• Filed: 06/14/2011
• Issued: 03/05/2013
• Est. Priority Date: 06/14/2011
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Ali, Ahmed Mohamed Abdelatty
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US13/159,734
• Publication Number:
  US 20120319877A1
• Time in Patent Office: 630 Days
• Field of Search: 341/118, 341/120, 341/155, 341/144, 341/161
• US Class Current: 341/118
• CPC Class Codes: H03M 1/1014 at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/1061 using digitally programmable trimming circuits
• CPC Class Codes: H03M 1/164 the steps being performed sequentially in series-connected stages H03M1/161 takes precedence

Abstract

An analog-to-digital converter system that includes a pipeline of successively-cascaded signal converters, each operating alternatively in a first circuit configuration and a second circuit configuration, an error estimator coupled to the pipeline to receive the digitized error for estimating an amplifier gain of the present signal converter stage, and a code aligner/corrector that temporally aligns and corrects the digital codes received from the successively-cascaded signal converters to provide a digital out of the ADC system.

Claims

1. An analog-to-digital converter (ADC) system for converting an input, comprising:

a pipeline including successively-cascaded signal converter stages, each signal converter stage including an analog-to-digital converter (ADC) for converting a portion of the input into digital codes and a multiplying digital-to-analog converter (MDAC) for outputting a residual portion of the input to a following signal converter stage, the MDAC including an amplifier having a summing node and operating alternatively in a first circuit configuration and a second circuit configuration, wherein

for a present signal converter stage, a summing node error is capacitively extracted under the first configuration of the MDAC of the present signal converter stage,

the extracted summing node error is amplified by the amplifier in a succeeding second configuration of the MDAC of the present signal converter stage to output an amplified error to a following signal converter stage, and

the amplified error is one of (a) amplified in a second configuration of following signal converter stages and (b) digitized in a first configuration by the ADC starting from one of the following signal converter stages,

an error estimator coupled to the pipeline to receive the digitized error for estimating an amplifier gain of the present signal converter stage, and

a code aligner/corrector that temporally aligns and corrects the digital codes received from the successively-cascaded signal converters to provide a digital out of the ADC system.

2. The ADC system of claim 1, wherein the error estimator calculates the amplifier gain based on the amplified error up to the one of the signal converters.

3. The ADC system of claim 1, wherein the MDAC in the each signal converter switches between the first and second circuit configurations via a plurality of switches controlled according to a first clock.

4. The ADC system of claim 3, wherein the error estimator is selectively coupled to the pipeline according to a second clock which is independent of the first clock.

5. The ADC system of claim 3, wherein the first circuit configuration occurs during one of a first half clock cycle and a second half clock cycle of the first clock, and the second circuit configuration occurs during an opposite half clock cycle of the first circuit configuration.

6. The ADC system of claim 1, wherein signal converter stages in the pipeline operates alternatively in the first and second configurations.

7. The ADC system of claim 1, wherein the summing node error of the present signal converter stage is amplified for three stages before error digitization starts.

8. The ADC system of claim 1, wherein the summing node error of the present signal converter stage is amplified for five stages before error digitization starts.

9. The ADC system of claim 1, wherein once the digitization starts at a signal converter stage, each following stage to the signal converter stage performs error digitization.

10. An analog-to-digital converter (ADC) system for converting an input, comprising:

a pipeline including successively-cascaded signal converter stages, each signal converter stage including an analog-to-digital converter (ADC) for converting a portion of the input into digital codes and a multiplying digital-to-analog converter (MDAC) for outputting a residual portion of the input to a following signal converter stage, the MDAC including an amplifier having a summing node and operating alternatively in a first circuit configuration and a second circuit configuration, wherein

for a present signal converter stage, a summing node error is capacitively extracted under the first configuration of the MDAC of the present signal converter stage,

the extracted summing node error is amplified by the amplifier in a succeeding second configuration of the MDAC of the present signal converter stage to output an amplified error to a following signal converter stage, and

the amplified error is one of (a) amplified in a second configuration of following signal converter stages and (b) digitized in a first configuration by the ADC starting from one of the following signal converter stages, and

an error estimator coupled to the pipeline to receive the digitized error for estimating an amplifier gain of the present signal converter stage,

wherein the error estimator calculates a gain voltage that controls the present amplifier to work at a maximum gain regardless of changes in current supply and temperature.

11. The ADC system of claim 10, wherein the error estimator calculates the amplifier gain based on the amplified error up to the one of the signal converters.

12. The ADC system of claim 10, further comprising a code aligner/corrector the uses the calculated amplifier gain to correct the digital output of the ADC.

13. The ADC system of claim 10, wherein the MDAC in the each signal converter switches between the first and second circuit configurations via a plurality of switches controlled according to a first clock.

14. The ADC system of claim 13, wherein the error estimator is selectively coupled to the pipeline according to a second clock which is independent of the first clock.

15. The ADC system of claim 13, wherein the first circuit configuration occurs during one of a first half clock cycle and a second half clock cycle of the first clock, and the second circuit configuration occurs during an opposite half clock cycle of the first circuit configuration.