Overvoltage and overcurrent protection scheme
First Claim
Patent Images
1. A method for protecting a transistor against overload, the method comprising:
- providing an input signal to a base terminal of a transistor for a first amount of time;
determining whether a system voltage of a system that includes the transistor is above a threshold operating voltage level, wherein when the system voltage is above the threshold operating voltage level, the first amount of time comprises a first predetermined amount of time, and wherein when the system voltage is below the threshold operating voltage level, the first amount of time comprises a second predetermined amount of time;
upon expiration of the first amount of time, making a determination of whether an overload condition exists at the transistor, wherein making a determination of whether an overload condition exists at the transistor comprises making a determination of whether a voltage level at a collector terminal of the transistor exceeds a threshold collector voltage level;
disabling the transistor for a second amount of time when the determination is that an overload condition exists at the transistor; and
providing the input signal to the base terminal upon expiration of the second amount of time.
1 Assignment
0 Petitions
Accused Products
Abstract
Disclosed are methods and corresponding systems to detect and prevent and/or eliminate overload conditions for a transistor. According to an embodiment, a method includes providing an input signal to a base terminal of a transistor for a first amount of time, determining if an overload condition exists at the transistor, disabling the transistor for a second amount of time when the overload condition exists at the transistor, and providing the communication signal to the base terminal upon expiration of the second amount of time. Additional overload conditions can be checked upon expiration of the second amount of time as well.
17 Citations
14 Claims
-
1. A method for protecting a transistor against overload, the method comprising:
-
providing an input signal to a base terminal of a transistor for a first amount of time; determining whether a system voltage of a system that includes the transistor is above a threshold operating voltage level, wherein when the system voltage is above the threshold operating voltage level, the first amount of time comprises a first predetermined amount of time, and wherein when the system voltage is below the threshold operating voltage level, the first amount of time comprises a second predetermined amount of time; upon expiration of the first amount of time, making a determination of whether an overload condition exists at the transistor, wherein making a determination of whether an overload condition exists at the transistor comprises making a determination of whether a voltage level at a collector terminal of the transistor exceeds a threshold collector voltage level; disabling the transistor for a second amount of time when the determination is that an overload condition exists at the transistor; and providing the input signal to the base terminal upon expiration of the second amount of time. - View Dependent Claims (2, 3)
-
-
4. A method for protecting a transistor against overload, the method comprising:
-
providing an input signal to a base terminal of a transistor for a first amount of time; upon expiration of the first amount of time, making a determination of whether an overload condition exists at the transistor; disabling the transistor for a second amount of time when the determination is that an overload condition exists at the transistor; providing the input signal to the base terminal upon expiration of the second amount of time; upon expiration of a third amount of time, making a determination of whether an additional overload condition exists at the transistor; disabling the transistor for a fourth amount of time when the determination is that an additional overload condition exists at the transistor; and providing the input signal to the base terminal upon expiration of the fourth amount of time. - View Dependent Claims (5, 6)
-
-
7. A circuit comprising:
-
a first signal line coupled to a collector terminal of a transistor; an overload protection module coupled between a second signal line and a base terminal of the transistor, the overload protection module including; means for applying a signal to the base terminal of a transistor for a first amount of time, the signal representative of a signal on the second signal line; means for making a determination of whether an overload condition exists at the transistor upon expiration of the first amount of time, wherein the means for making a determination of whether an overload condition exists at the transistor comprises means for making a determination of whether a voltage level at the collector terminal of the transistor exceeds a threshold collector voltage level; means for disabling the transistor for a second amount of time when the determination is that an overload condition exists at the transistor; and means for applying the signal to the base terminal upon expiration of the second amount of time and means for determining a system voltage of the circuit is above a threshold operating voltage level, wherein when the system voltage is above a threshold operating voltage level, the first amount of time comprises a first predetermined amount of time, and wherein when the system voltage is below a threshold operating voltage level, the first amount of time comprises a second predetermined amount of time. - View Dependent Claims (8, 9)
-
-
10. A circuit comprising:
-
a first signal line coupled to a collector terminal of a transistor; an overload protection module coupled between a second signal line and a base terminal of the transistor, the overload protection module including; means for applying a signal to the base terminal of a transistor for a first amount of time, the signal representative of a signal on the second signal line; means for making a determination of whether an overload condition exists at the transistor upon expiration of the first amount of time; means for disabling the transistor for a second amount of time when the determination is that an overload condition exists at the transistor; means for applying the signal to the base terminal upon expiration of the second amount of time; and means for making a determination, upon expiration of a third amount of time, of whether an additional overload condition exists at the transistor; means for disabling the transistor for a fourth amount of time when the additional overload condition exists at the transistor; and means for applying the signal on the second signal line to the base terminal upon expiration of the fourth amount of time. - View Dependent Claims (11, 12)
-
-
13. A field programmable gate array (FPGA) having an association of logic gates, wherein the logic gates are wired to perform functions, the functions comprising:
-
providing an input signal to a base terminal of a transistor for a first amount of time; upon expiration of the first amount of time, making a determination of whether an overload condition exists at the transistor; disabling the transistor for a second amount of time when the determination is that an overload condition exists at the transistor; providing the input signal to the base terminal upon expiration of the second amount of time; and upon expiration of a third amount of time, making a determination of whether an additional overload condition exists at the transistor; disabling the transistor for a fourth amount of time when the determination is that an additional overload condition exists at the transistor; and providing the communication signal to the base terminal upon expiration of the fourth amount of time. - View Dependent Claims (14)
-
Specification