Memory module with termination component
First Claim
1. A module comprising:
- a first memory device having a memory array;
a first signal line coupled to the first memory device, the first signal line to provide first data to the first memory device, the first data to be stored in the memory array of the first memory device during a write operation;
a second memory device having a memory array;
a second signal line coupled to the second memory device, the second signal line to provide second data to the second memory device, the second data to be stored in the memory array of the second memory device during the write operation;
a first termination component; and
a control signal path coupled to the first memory device, the second memory device, and the first termination component such that a write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the first termination component, wherein the write command specifies the write operation.
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Accused Products
Abstract
A module having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data thereto, the first data to be stored in a memory array of the first memory device during a write operation. A second signal line is coupled to the second memory device to provide thereto, the second data to be stored in a memory array of the second memory device during the write operation. A control signal path is coupled to the first memory device, the second memory device and the termination component such that a write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the first termination component, wherein the write command specifies the write operation.
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Citations
11 Claims
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1. A module comprising:
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a first memory device having a memory array; a first signal line coupled to the first memory device, the first signal line to provide first data to the first memory device, the first data to be stored in the memory array of the first memory device during a write operation; a second memory device having a memory array; a second signal line coupled to the second memory device, the second signal line to provide second data to the second memory device, the second data to be stored in the memory array of the second memory device during the write operation; a first termination component; and a control signal path coupled to the first memory device, the second memory device, and the first termination component such that a write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the first termination component, wherein the write command specifies the write operation. - View Dependent Claims (2, 3, 4)
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5. A module comprising:
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a first rank of memory devices including a first memory device, and a second memory device; a second rank of memory devices including a third memory device, and a fourth memory device; a first data signal line coupled to the first memory device and the third memory device; a second data signal line coupled to the second memory device and the fourth memory device; a termination component; and a signal path coupled to the first rank of memory devices and the second rank of memory devices memory device, and the termination component such that control information propagating on the control signal path propagates past the first rank of memory devices and the second rank of memory devices before reaching the termination component. - View Dependent Claims (6, 7)
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8. A module comprising:
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a first memory device, a second memory device, a third memory device, and a fourth memory device; a first signal line coupled to the first memory device and the third memory device, the first signal line being dedicated to data transfers involving one of the first memory device and the third memory device; a second signal line coupled to the second memory device and the fourth memory device, the second signal line being dedicated to data transfers involving one of the second memory device and the fourth memory device; a first termination component; and a control signal path coupled to the first memory device, second memory device, third memory device, fourth memory device, and the first termination component such that a command propagating on the control signal path propagates past the first memory device before reaching the third memory device, propagates past the third memory device before reaching the second memory device, propagates past the second memory device before reaching the fourth memory device, and propagates past the fourth memory device before reaching the first termination component. - View Dependent Claims (9, 10, 11)
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Specification