Non-volatile memory with dynamic multi-mode operation
First Claim
1. A method comprising:
- receiving a request that includes a logical address;
mapping the logical address to a corresponding physical address within a flash memory array; and
issuing i) a first type of program command when the physical address is within a first subdivision of the flash memory array; and
ii) a second different type of program command when the physical address is within a second subdivision of the flash memory array, the first subdivision being different than the second subdivision.
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Abstract
A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist within the same memory array. One or more tag bits stored in each page of the memory is used to indicate the type of storage mode used for storing the data in the corresponding subdivision, where a subdivision can be a bank, block or page. A controller monitors the number of program-erase cycles corresponding to each page for selectively changing the storage mode in order to maximize lifespan of any subdivision of the multi-mode flash memory device.
54 Citations
20 Claims
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1. A method comprising:
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receiving a request that includes a logical address; mapping the logical address to a corresponding physical address within a flash memory array; and issuing i) a first type of program command when the physical address is within a first subdivision of the flash memory array; and
ii) a second different type of program command when the physical address is within a second subdivision of the flash memory array, the first subdivision being different than the second subdivision. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method carried out within a flash memory device, the method comprising:
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receiving a first external command; decoding the first external command to issue a corresponding first internal control command to execute a first program operation in accordance with a first algorithm; receiving a second external command; and decoding the second external command to issue a corresponding second internal control command to execute a second program operation in accordance with a second algorithm, the first algorithm and the second algorithm each associated with different specific voltage levels and timings of control signals. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A system comprising:
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a flash memory device including a flash memory array having at least a first subdivision configured in a first storage mode and a second subdivision configured in a second storage mode, the first storage mode being different than the second storage mode; and a controller configured to receive a request from a host system, the controller including a translator configured to map a logical address provided by the host system to a corresponding physical address in the flash memory device, the controller being further configured to issue a command to the flash memory device which is coupled to the controller, and the flash memory device being configured to execute, in response to the command, a read or program operation in accordance with i) a first algorithm when the logical address corresponds to a first physical address within the first subdivision; and
ii) a second different algorithm when the logical address corresponds to a second physical address within the second subdivision. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification