Semiconductor memory having both volatile and non-volatile functionality and method of operating
First Claim
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1. A semiconductor memory cell comprising:
- a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory;
a first region in electrical contact with said floating body region;
a second region in electrical contact with said floating body region and spaced apart from said first region;
a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of data stored as said volatile memory and store said data as nonvolatile memory indicative of said state of the memory cell; and
a control gate positioned above the floating gate or trapping layer,wherein said charge stored in said floating body region determines a charge stored in said floating gate or trapping layer upon interruption of power to the memory cell.
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Abstract
Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate, a floating body to store data in volatile memory and a floating gate or trapping layer configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell.
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Citations
21 Claims
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1. A semiconductor memory cell comprising:
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a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of data stored as said volatile memory and store said data as nonvolatile memory indicative of said state of the memory cell; and a control gate positioned above the floating gate or trapping layer, wherein said charge stored in said floating body region determines a charge stored in said floating gate or trapping layer upon interruption of power to the memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor memory cell comprising:
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a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of data stored as said volatile memory and store said data as nonvolatile memory indicative of said state of the memory cell; and a control gate positioned above the floating gate or trapping layer, wherein said state stored in said floating body region determines a current flowing through said semiconductor memory cell. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A method of operating a memory cell to economize power usage, wherein the memory cell has a floating body for storing data as volatile memory and a floating gate or trapping layer for storing data as non-volatile memory, the method comprising:
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monitoring activity of said cell; and after a predetermined period of time during which said cell has remained idle, performing a shadowing operation thereby storing a state of the cell in non-volatile memory. - View Dependent Claims (17, 18, 19, 20)
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21. A memory device comprising:
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a plurality of semiconductor memory cells, each said memory cell having; a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of data stored as said volatile memory and store said data as nonvolatile memory indicative of said state of the memory cell; and a control gate positioned above the floating gate or trapping layer; and wherein said transfer of data to said floating gate or trapping layer occurs in said memory cells in a parallel, non-algorithmic manner.
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Specification