TD-SCDMA uplink processing for synchronization of signals at base station receiver

• US 8,391,267 B2
• Filed: 08/19/2008
• Issued: 03/05/2013
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Ponnathota, Prahallada, Howe, Thomas F.
• Primary Examiner(s): Nooristany, Sulaiman
• Application Number:
  US12/194,521
• Publication Number:
  US 20090161649A1
• Time in Patent Office: 1,659 Days
• Field of Search: 370/342
• US Class Current: 370/342
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 2201/70707 Efficiency-related aspects
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables

Abstract

A wireless system includes a TTI memory architecture in which encoded data are stored in a memory at a rate of one block of encoded data per transmission time interval (TTI), TTI being selected from a set of predetermined values, the memory including memory lines each having a predetermined number of bits that is determined according to the set of predetermined TTI values. For every block of data in which the end of the block of data does not align with an end of a last memory line occupied by the block of data, one or more padded bits are stored after the end of the block of data to the end of the last memory line occupied by the block of data so the last memory line is filled with a portion of the block of data and the one or more padded bits. The block of data and the padded bits are read in one or more equal sized segments.

Claims

1. A method comprising:

in a wireless communication device that implements radio frame equalization in compliance with a telecommunications standard that specifies a transmission time interval to be 10*2^N ms, N being any integer ranging from 0 to 3,

storing a block of channel encoded data of a transport channel in a memory comprising memory lines each having 8 bits;

if the block of channel encoded data has a number of bits that is not an integer multiple of 8, storing one or more padded bits after an end of the block of channel encoded data to an end of a last memory line occupied by the block of channel encoded data;

reading the block of channel encoded data and the padded bits from the memory in equal sized segments;

wherein a group of registers is provided to store time slot configuration parameters includes writing five sets of time slot configuration parameters for configuring a chip rate processing unit to process five uplink time slots of a sub-frame; and

processing data using the chip rate processing unit, including performing at least one of spreading data, scrambling data, and combining data from multiple physical channels to prepare the data for uplink transmission;

wherein the telecommunications standard comprises Time Division-Synchronous Code Division Multiple Access standard.

2. The method of claim 1, further comprising, for each active transport channel, storing a block of channel encoded data of the active transport channel in the memory per transmission time interval associated with the respective active transport channel.

3. The method of claim 1 in which storing one or more padded bits comprises at least one of storing one or more bits having bit values all equal to 0, storing one or more bits having bit values all equal to 1, and storing one or more bits having random bit values.

4. The method of claim 1 in which storing the one or more padded bits after the end of the block of channel encoded data to the end of the last memory line occupied by the block of channel encoded data is performed without calculating a number of padded bits to be stored.

5. A method comprising:

storing encoded data in a memory at a rate of one block of encoded data per transmission time interval (TTI), TTI being selected from a set of predetermined values, the memory comprising memory lines each having a predetermined number of bits that is determined according to the set of predetermined TTI values;

for every block of data in which the end of the block of data does not align with an end of a last memory line occupied by the block of data, storing one or more padded bits after the end of the block of data to the end of the last memory line occupied by the block of data so the last memory line is filled with a portion of the block of data and the one or more padded bits;

reading the block of data and the padded bits in one or more equal sized segments,

in which each TTI value is equal to 10*2^N ms, N being an integer ranging from 0 to 3, and each memory line has 8 bits;

wherein a group of registers is provided to store time slot configuration parameters includes writing five sets of time slot configuration parameters for configuring a chip rate processing unit to process five uplink time slots of a sub-frame; and

processing data using the chip rate processing unit, including performing at least one of spreading data, scrambling data, and combining data from multiple physical channels to prepare the data for uplink transmission;

wherein storing the encoded data, storing the padded bits, and reading the block of data and padded bits comply with Time Division-Synchronous Code Division Multiple Access standard.

6. The method of claim 5, further comprising performing bit rate processing front end processing on input data to generate the encoded data.

7. The method of claim 5, further comprising performing bit rate processing back end processing on the segments of data read from the memory.

8. The method of claim 5 in which storing the one or more padded bits after the end of the block of data to the end of the last memory line occupied by the block of channel encoded data is performed without calculating a number of padded bits to be stored.

9. An apparatus comprising:

a memory comprising memory lines, each memory line having a predetermined number of bits;

a first circuitry to store blocks of data of a transport channel associated with a wireless transmission link in the memory, and for each of the blocks of data that has a number of bits that is not an integer multiple of the predetermined number, storing one or more padded bits after an end of the block of data to an end of a last memory line occupied by the block of data;

a second circuitry to read the block of data and the padded bits from the memory in one or more equal sized segments;

a chip rate processing unit to process data, including performing at least one of spreading data, scrambling data, and combining data from multiple physical channels to prepare the data for uplink transmission;

wherein a group of registers is provided to store time slot configuration parameters includes to store five sets of time slot configuration parameters for configuring the chip rate processing unit to process five uplink time slots of a sub-frame,

wherein the first circuitry processes data in compliance with a telecommunications standard that specifies the transmission time interval to be 10*2^N ms, N being any integer ranging from 0 to 3, and each memory line has 8 bits; and

wherein the first and second circuitry process data in compliance with Time Division-Synchronous Code Division Multiple Access standard.

10. The apparatus of claim 9 in which the first circuitry stores a block of data for each active transport channel associated with the wireless transmission link to the memory per transmission time interval associated with the respective transport channel.

11. The apparatus of claim 9 in which the second circuitry reads a segment of data from the memory per 10 ms time interval.

12. The apparatus of claim 9 in which the first circuitry stores the padded bits after the blocks of data in the memory without performing a calculation on the number of padded bits to be stored after the end of the blocks of data.

13. The apparatus of claim 9 in which the first circuitry comprises a channel encoder.

14. The apparatus of claim 9 in which the first circuitry comprises a bit rate processing front end processing unit.

15. The apparatus of claim 9 in which the second circuitry comprises an interleaver that interleaves the data read from the memory.

16. The apparatus of claim 9 in which the second circuitry comprises a bit rate processing back end processing unit.

17. The apparatus of claim 9 in which storing one or more padded bits comprises storing at least one of one or more bits having bit values all equal to 0, one or more bits having bit values all equal to 1, and one or more bits having random bit values.

18. A wireless chipset for processing data for uplink transmission, the wireless chipset comprising:

a transmission timing interval (TTI) memory comprising memory lines, each memory line having a predetermined number of bits;

a bit rate processing (BRP) front end processing unit to store a block of encoded data in the TTI memory per TTI for each active transport channel, and for each of the blocks of encoded data that has a number of bits that is not an integer multiple of the predetermined number, storing one or more padded bits after an end of the block of encoded data to fill a last memory line occupied by the block of encoded data;

a BRP back end processing unit to read each block of encoded data and associated padded bits from the memory in one or more equal sized segments,

a chip rate processing unit to process data, including performing at least one of spreading data, scrambling data, and combining data from multiple physical channels to prepare the data for uplink transmission;

wherein a group of registers is provided to store time slot configuration parameters includes to store five sets of time slot configuration parameters for configuring the chip rate processing unit to process five uplink time slots of a sub-frame,

wherein the BRP front end processing unit processes data in compliance with a telecommunications standard that specifies the transmission time interval to be 10*2^N ms, N being any integer ranging from 0 to 3, and each memory line has 8 bits; and

wherein the BRP front end processing unit and BRP back end processing unit process data in compliance with Time Division-Synchronous Code Division Multiple Access standard.

19. The wireless chipset of claim 18 in which the bit rate processing front end processing unit stores the one or more padded bits after the end of the block of encoded data to fill the last memory line without performing a calculation on the number of padded bits to be stored after the end of the block of encoded data.

20. An apparatus comprising:

a memory comprising memory lines, each memory line having a predetermined number of bits;

a first circuitry to store encoded data in the memory at a rate of one block of encoded data per transmission time interval (TTI), TTI being selected from a set of predetermined values;

means for storing padded bits in the memory, in which for every block of encoded data where the end of the block of encoded data does not align with an end of a last memory line occupied by the block of encoded data, padded bits are stored after the end of the block of data to the end of the last memory line occupied by the block of data without calculating a number of padded bits;

a second circuitry to read the block of data and the padded bits in one or more equal sized segments;

a chip rate processing unit to process data, including performing at least one of spreading data, scrambling data, and combining data from multiple physical channels to prepare the data for uplink transmission;

wherein a group of registers is provided to store time slot configuration parameters includes to store five sets of time slot configuration parameters for configuring the chip rate processing unit to process five uplink time slots of a sub-frame,

wherein the first circuitry processes data in compliance with a telecommunications standard that specifies the transmission time interval to be 10*2^N ms, N being any integer ranging from 0 to 3, and each memory line consists of 8 bits; and

wherein the first and second circuitry process data in compliance with Time Division-Synchronous Code Division Multiple Access standard.