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Deterministic finite automata (DFA) processing

  • US 8,392,590 B2
  • Filed: 09/07/2005
  • Issued: 03/05/2013
  • Est. Priority Date: 09/10/2004
  • Status: Active Grant
First Claim
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1. A network processor, comprising:

  • at least one processor core;

    a deterministic finite automata (DFA) module operating asynchronously to the at least one processor core, the DFA module traversing a plurality of nodes of at least one DFA graph stored in a non-cache memory that is;

    i) external to the network processor and ii) sized to accommodate the at least one DFA graph having a number of nodes for searching for multiple patterns in one traversal of the at least one DFA graph, the DFA module including a plurality of DFA thread engines associated in a shared configuration with the at least one processor core;

    and responsive to instructions for traversing the plurality of nodes of the at least one DFA from the at least one processor core, with packet data stored in a cache-coherent memory, each of the plurality of DFA thread engines is configured to;

    traverse at least one DFA graph independent of others of the plurality of DFA thread engines traversing DFA graphs including the at least one DFA graph,fetch the packet data stored in the cache-coherent memory,in response to each byte of packet data fetched from the cache-coherent memory, issue an instruction to access and load a next node of the at least one DFA graph from the non-cache memory to traverse the next node of the at least one DFA graph, andwrite intermediate and final results of traversing the at least one DFA graph to the cache-coherent memory.

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