Network on chip
First Claim
1. A network on chip (‘
- NOC’
) comprising;
integrated processor (‘
IP’
) blocks, routers, memory communications controllers, and network interface controllers;
each IP block adapted to a router through a memory communications controller and a network interface controller;
each memory communications controller controlling communications between an IP block and memory;
each network interface controller controlling inter-IP block communications through routers; and
at least one IP block further comprising a computer processor and an L1, write-through data cache comprising high speed local memory on the IP block, the cache controlled by a cache controller having a cache line replacement policy, the cache controller configured to lock segments of the cache, the computer processor configured to store thread-private data in main memory off the IP block, the computer processor further configured to store thread-private data on a segment of the L1 data cache, the segment locked against replacement upon cache misses under the cache controller'"'"'s replacement policy, the segment further locked against write-through to main memory, wherein the cache controller configured to lock segments of the cache further comprises the cache controller configured to load and lock a cache line in a segment upon the first load of the cache line by a thread owning private data and based on the thread'"'"'s private data.
1 Assignment
0 Petitions
Accused Products
Abstract
A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; and at least one IP block also including a computer processor and an L1, write-through data cache comprising high speed local memory on the IP block, the cache controlled by a cache controller having a cache line replacement policy, the cache controller configured to lock segments of the cache, the computer processor configured to store thread-private data in main memory off the IP block, the computer processor further configured to store thread-private data on a segment of the L1 data cache, the segment locked against replacement upon cache misses under the cache controller'"'"'s replacement policy, the segment further locked against write-through to main memory.
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Citations
18 Claims
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1. A network on chip (‘
- NOC’
) comprising;integrated processor (‘
IP’
) blocks, routers, memory communications controllers, and network interface controllers;
each IP block adapted to a router through a memory communications controller and a network interface controller;
each memory communications controller controlling communications between an IP block and memory;
each network interface controller controlling inter-IP block communications through routers; andat least one IP block further comprising a computer processor and an L1, write-through data cache comprising high speed local memory on the IP block, the cache controlled by a cache controller having a cache line replacement policy, the cache controller configured to lock segments of the cache, the computer processor configured to store thread-private data in main memory off the IP block, the computer processor further configured to store thread-private data on a segment of the L1 data cache, the segment locked against replacement upon cache misses under the cache controller'"'"'s replacement policy, the segment further locked against write-through to main memory, wherein the cache controller configured to lock segments of the cache further comprises the cache controller configured to load and lock a cache line in a segment upon the first load of the cache line by a thread owning private data and based on the thread'"'"'s private data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
- NOC’
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10. A method of data processing with a network on chip (‘
- NOC’
), the NOC comprising IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller,at least one IP block further comprising a computer processor and an L1, write-through data cache comprising high speed local memory on the IP block, the computer processor configured to store thread-private data in main memory off the IP block, the cache controlled by a cache controller having a cache line replacement policy, the method comprising; controlling by each memory communications controller communications between an IP block and memory, controlling by each network interface controller inter-IP block communications through routers, locking, by the cache controller, a segment of the L1 data cache, the segment locked against replacement upon cache misses under the cache controller'"'"'s replacement policy, the segment further locked against write-through to main memory; loading and locking a cache line in the segment upon the first load of the cache line by a thread owning private data and based on the thread'"'"'s private data; and storing, by the computer processor, the thread-private data on the segment of the L1 data cache. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
- NOC’
Specification