System and method for read synchronization of memory modules

• US 8,392,686 B2
• Filed: 09/18/2008
• Issued: 03/05/2013
• Est. Priority Date: 12/29/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M., LaBerge, Paul
• Primary Examiner(s): Rojas, Midys
• Application Number:
  US12/233,492
• Publication Number:
  US 20090013143A1
• Time in Patent Office: 1,629 Days
• Field of Search: 713/500, 713/502, 713/501, 713/400, 711/167, 711/154, 711/170
• US Class Current: 711/167
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234

Abstract

A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.

Claims

1. A memory read synchronization system, comprising:

a storage device having an input port operable to receive read data signals in response to a first clock signal, the storage device having an output port operable to output the read data signals in response to a second clock signal; and

a timing comparison component coupled to the storage device, the timing comparison component operable to compare a first time in which the read data signals provided by a memory device are input to the storage device with a second time in which the read data signals are output the storage device, the timing comparison component further operable to generate an adjust signal in response to the comparison that is used to adjust the timing at which subsequent read data signals are provided by the memory device to be input to the storage device.

2. The memory read synchronization system of claim 1 further comprises a write pointer coupled to the storage device, the write pointer being incremented in response to the read data being input to the storage device.

3. The memory read synchronization system of claim 1 further comprises a read pointer coupled to the storage device, the read pointer being incremented in response to the read data being output the storage device.

4. The memory read synchronization system of claim 1 wherein the timing comparison component compares the read pointer and the write pointer to generate the adjust signal.

5. The memory read synchronization system of claim 1 wherein the clock signal is a core clock signal.

6. A memory read synchronization module, comprising:

a storage device operable to receive read data signal from a memory device and increment a write pointer in response to a first clock signal, the storage device further operable to output the read data signal and increment a read pointer in response to a second clock signal;

a comparator coupled to the storage device, the comparator operable to compare the write pointer and the read pointer, the comparator operable to generate an adjust signal in response to the comparison; and

a signal generator coupled to the comparator and configured to receive the adjust signal, the signal generator further configured to generate signals for controlling an operation of a memory device in response to the adjust signal.

7. The memory read synchronization module of claim 6 wherein the signal generator is one of a direct memory access engine or memory sequencer.

8. The memory read synchronization module of claim 6 wherein the storage device is circular buffer.

9. A method of coupling read data from a memory device to a storage device and outputting the read data from the storage device, comprising:

latching read data into the storage device in response to a first clock signal;

outputting the read data from the storage device in response to a second clock signal;

comparing the timing in which the read data is latched by the first clock signal and the timing in which the read data is output by the second clock signal;

generating an adjust signal in response to the comparison; and

adjusting the time at which subsequent read data are provided to be latched into the storage device based on the adjust signal.

10. The method of claim 9 wherein the storage device is a first in first out buffer.

11. The method of claim 9 further comprising incrementing a write pointer in response to the first clock signal and incrementing a read pointer in response to the second clock signal.

12. The method of claim 11 wherein the act of comparing the timing in which the read data is latched by the first clock signal and the timing in which the read data is output by the second clock comprises comparing the read pointer with the write pointer.

13. The method of claim 9 wherein the first clock signal is provided by a first clock and the second clock signal is provided by a second clock, the first clock being different from the second clock.