Solid state memory formatting

• US 8,392,687 B2
• Filed: 01/21/2009
• Issued: 03/05/2013
• Est. Priority Date: 01/21/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Asnaashari, Mehdi, Benson, William E.
• Primary Examiner(s): Dudek, Jr., Edward
• Assistant Examiner(s): Fishburn, John P
• Application Number:
  US12/356,725
• Publication Number:
  US 20100185802A1
• Time in Patent Office: 1,504 Days
• Field of Search: 711/170, 711/E12.007
• US Class Current: 711/170
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0643 Management of files
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

The present disclosure includes methods and devices for solid state drive formatting. One device embodiment includes control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells. The memory arrays are formatted by the control circuitry that is configured to write system data to the number of memory arrays, where the system data ends at a physical block boundary; and write user data to the number of memory arrays, where the user data starts at a physical block boundary.

Claims

1. A memory controller, comprising:

control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells and wherein the control circuitry formats each memory array by;

writing system data to the number of memory arrays, where the system data ends at a physical block boundary of a first block, by including a padding of memory cells that do not contain data so that the system data ends at the physical block boundary of the first block; and

writing user data to the number of memory arrays, where the user data starts at a physical block boundary of a second block, wherein the first block is a different block than the second block.

2. The memory controller of claim 1, wherein the number of memory arrays include a portion for system data and a portion for user data.

3. The memory controller of claim 1, wherein the padding of memory separates a first portion of the system data from a second portion of the system data such that the system data ends at the physical block boundary of the first block.

4. The memory controller of claim 1, wherein an indication of one or more physical parameters of the number of memory arrays is stored in memory in the control circuitry.

5. The memory controller of claim 4, wherein the one or more physical parameters of the number of memory arrays include array size, page size, block size, and memory cell type.

6. The memory controller of claim 1, wherein the control circuitry formats each memory array by writing the system data so that the system data includes a file allocation table that ends at the physical block boundary of the first block.

7. The memory controller of claim 1, wherein the control circuitry formats each memory array by writing the system data so that the system data includes reserved data and a file allocation table and so that a padding of erased memory cells between reserved data and the file allocation table causes the file allocation table to end at the physical block boundary of the first block.

8. The memory controller of claim 1, wherein the control circuitry formats each memory array by writing the system data so that the system data includes a first file allocation table and a second file allocation table and so that a padding of erased memory cells is between the first file allocation table and the second file allocation table.

9. The memory controller of claim 1, wherein the system data includes a partition boot record, reserved data, a first file allocation table, and a second file allocation table.

10. The memory controller of claim 1, wherein the control circuitry formats each memory array by writing the system data so that the system data includes reserved data, a first file allocation table, and a second file allocation table and so that a padding of erased memory cells between reserved data and the first file allocation table causes the second file allocation table to end at the physical block boundary of the first block.

11. The memory controller of claim 1, wherein the control circuitry formats each memory array by writing user data starting at the physical block boundary based of the second block, at least partially, on one or more physical parameters of the particular memory array and a modulus for writing to the particular memory array.