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Solid state memory formatting

  • US 8,392,687 B2
  • Filed: 01/21/2009
  • Issued: 03/05/2013
  • Est. Priority Date: 01/21/2009
  • Status: Active Grant
First Claim
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1. A memory controller, comprising:

  • control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells and wherein the control circuitry formats each memory array by;

    writing system data to the number of memory arrays, where the system data ends at a physical block boundary of a first block, by including a padding of memory cells that do not contain data so that the system data ends at the physical block boundary of the first block; and

    writing user data to the number of memory arrays, where the user data starts at a physical block boundary of a second block, wherein the first block is a different block than the second block.

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