Memory arrays and methods of fabricating memory arrays

• US 8,394,699 B2
• Filed: 07/01/2010
• Issued: 03/12/2013
• Est. Priority Date: 08/21/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Haller, Gordon A., Tang, Sanh D.
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US12/828,915
• Publication Number:
  US 20100273303A1
• Time in Patent Office: 985 Days
• Field of Search: 438/259, 438/270, 438/589, 438244-254, 438/E27.096, 438/E27.055, 438/E27.58, 438/E27.57
• US Class Current: 438/259
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are hard wired together. A conductive data line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two. Other aspects and implementations are contemplated, including methods of fabricating memory arrays.

Claims

1. A method of fabricating a memory array, comprising:

forming alternating lines of active area regions and trench isolation regions within semiconductive material;

etching a series of racetrack-shaped trenches into the active area regions and the trench isolation regions generally orthogonal to the alternating lines of active area regions and trench isolation regions;

forming conductive material within the racetrack-shaped trenches to form a pair of electrically connected word lines in each of the racetrack-shaped trenches;

forming source/drain regions within the active area regions laterally internal of the racetrack-shaped trenches and laterally external of the racetrack-shaped trenches;

forming conductive data lines in electrical connection with the source/drain regions formed laterally external of the racetrack-shaped trenches; and

forming charge storage devices in electrical connection with the source/drain regions formed laterally internal of the racetrack-shaped trenches.

2. A method of fabricating a memory array, comprising:

forming alternating lines of active area regions and trench isolation regions within semiconductive material;

etching a series of pairs of trenches into the active area regions and the trench isolation regions generally orthogonal to the alternating lines of active area regions and trench isolation regions;

etching interconnecting trenches into the semiconductive material, each of the interconnecting trenches interconnecting individual of the trenches of each pair of trenches;

forming conductive material within the pairs of trenches and the interconnecting trenches to form a pair of electrically connected word lines in each of the pairs of trenches;

forming source/drain regions within the active area regions intermediate individual ones of the trenches of each pair of trenches and laterally external of individual ones of the trenches of each pair of trenches;

forming conductive data lines in electrical connection with the source/drain regions formed laterally external of individual ones of the trenches of each pair of trenches; and

forming charge storage devices in electrical connection with the source/drain regions formed intermediate individual ones of the trenches of each pair of trenches.

3. The method of claim 2 wherein etching the series of pairs of trenches and etching the interconnecting trenches comprises a common masking step.

4. The method of claim 2 wherein etching the series of pairs of trenches and etching the interconnecting trenches comprises a common etching step.

5. The method of claim 2 wherein forming the conductive material comprises depositing at least some conductive material within the pairs of trenches and the interconnecting trenches at the same time.

6. The method of claim 2 wherein etching the interconnecting trenches comprises etching only one interconnecting trench for each pair of trenches.

7. The method of claim 2 wherein etching the interconnecting trenches comprises etching only two interconnecting trenches for each pair of trenches.

8. The method of claim 2 wherein etching the interconnecting trenches comprises etching multiple interconnecting trenches for each pair of trenches.

9. A method of fabricating a memory array, comprising:

forming alternating lines of active area regions and trench isolation regions within semiconductive material;

etching a series of pairs of trenches into the active area regions and the trench isolation regions generally orthogonal to the alternating lines of active area regions and trench isolation regions;

forming conductive material within the pairs of trenches to form a pair of word lines in each of the pairs of trenches;

forming source/drain regions within the active area regions intermediate individual ones of the trenches of each pair of trenches and laterally external of individual ones of the trenches of each pair of trenches;

forming conductive data lines in electrical connection with the source/drain regions formed laterally external of individual ones of the trenches of each pair of trenches; and

forming charge storage devices in electrical connection with the source/drain regions formed intermediate individual ones of the trenches of each pair, wherein individual memory cells of the memory array each comprise a respective one of the source/drain regions formed intermediate the respective pair of trenches within which the respective pair of word lines is formed, a respective two of the source/drain regions formed laterally external of the respective pair of trenches within which the respective pair of word lines is formed, and the charge storage device that is in electrical connection with the respective source/drain region formed intermediate the respective pair of trenches within which the respective pair of word lines is formed.

10. The method of claim 9 comprising:

etching interconnecting trenches into the semiconductive material, wherein each of the interconnecting trenches interconnects individual ones of the trenches of each respective pair of trenches; and

forming conductor material within the interconnecting trenches to electrically connect respective individual word lines within each respective pair of word lines.

11. The method of claim 9 comprising depositing peripheral circuitry gate material within memory array area and within peripheral circuitry area prior to the etching of the series of pairs of trenches, the etching of the series of pairs of trenches being conducted through the peripheral circuitry gate material that is within the memory array area prior to patterning the peripheral circuitry gate material to form transistor gates in the peripheral circuitry area.

12. The method of claim 9 wherein the forming of the conductive data lines comprises:

forming an interlevel dielectric and contact openings therethrough to the source/drain regions formed laterally external of individual ones of the trenches of each pair of trenches; and

depositing a conductor material within the contact openings and forming the conductive data lines from the conductor material.

13. The method of claim 12 wherein the forming of the conductive data lines from the conductor material comprises subtractive patterning and etch of the conductor material.

14. The method of claim 12 comprising depositing an insulative material over the conductor material prior to the forming of the conductive data lines from the conductor material.

15. The method of claim 12 comprising depositing an insulative material in physical touching contact with the conductor material after the forming of the conductive data lines from the conductor material.

16. The method of claim 12 wherein the forming of the conductive data lines from the conductor material comprises etching of the conductor material to recess the conductor material within the contact openings.

17. The method of claim 16 comprising forming insulative material within the contact openings over recessed conductor material.