Printable semiconductor structures and related methods of making and assembling

• US 8,394,706 B2
• Filed: 10/11/2011
• Issued: 03/12/2013
• Est. Priority Date: 06/04/2004
• Status: Active Grant

• Current Assignee: Board of Trustees of The University of Illinois
• Original Assignee: Board of Trustees of The University of Illinois
• Inventors: Nuzzo, Ralph G., Rogers, John A., Menard, Etienne, Lee, Keon Jae, Khang, Dahl-Young, Sun, Yugang, Meitl, Matthew, Zhu, Zhengtao, Ko, Heung Cho, Mack, Shawn
• Primary Examiner(s): Coleman, William D
• Application Number:
  US13/270,954
• Publication Number:
  US 20120083099A1
• Time in Patent Office: 518 Days
• Field of Search: 438/458, 257/E21.599
• US Class Current: 438/458
• CPC Class Codes: B81C 2201/0185 Printing, e.g. microcontact printing
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02628 using solutions
• CPC Class Codes: H01L 21/30 Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 manufacture of electrodes thereon H01L21/28
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/66265 Thin film bipolar transistors H01L29/66242 takes precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/72 Transistor-type devices, i.e. able to continuously respond to applied control signals
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78681 : having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 31/0392 : including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate textured substrates H01L31/02366
• CPC Class Codes: H01L 31/03925 : including AIIBVI compound materials, e.g. CdTe, CdS
• CPC Class Codes: H01L 31/03926 : comprising a flexible substrate
• CPC Class Codes: H01L 31/18 : Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• CPC Class Codes: H01L 31/1804 : comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/547 : Monocrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices.

Claims

1. A method for registered assembly of a plurality of printable semiconductor elements on a receiving surface of a substrate, said method comprising the steps of:

providing a plurality of printable semiconductor structures having preselected spatial orientations relative to each other;

wherein each of said printable semiconductor structures comprises a printable semiconductor element, and a bridge element connected to said printable semiconductor element and connected to a mother wafer, wherein each of said printable semiconductor elements and said bridge elements are at least partially undercut from said mother wafer;

contacting said printable semiconductor elements with a transfer device having a contact surface, wherein contact between said contact surface and said printable semiconductor elements binds at least a portion of said printable semiconductor elements to said contact surface of said transfer device;

moving said transfer device in a manner resulting in the fracture of at least a portion of said bridge elements, thereby providing for registered transfer of at least a portion of said printable semiconductor elements from said mother wafer to said transfer device, thereby forming said contact surface having at least a portion of said printable semiconductor elements disposed thereon;

contacting said receiving surface of said substrate with said printable semiconductor elements disposed on said contact surface; and

separating said contact surface of said transfer device and said printable semiconductor elements, wherein said printable semiconductor elements are transferred onto said receiving surface, thereby providing for registered assembly of said plurality of printable semiconductor elements on said receiving surface of said substrate.

2. The method of claim 1, wherein said relative spatial orientations of said printable semiconductor elements assembled on said receiving surface are maintained to within 5 microns.

3. The method of claim 1, wherein said relative spatial orientations of said printable semiconductor elements assembled on said receiving surface are maintained to within 0.1 microns.

4. The method of claim 1, wherein said printable semiconductor elements are assembled on to specific regions of said receiving substrate preselected to within 5 microns.

5. The method of claim 1, wherein said printable semiconductor elements are assembled on to specific regions of said receiving substrate preselected to within 500 nanometers.

6. The method of claim 1, wherein said steps of contacting said printable semiconductor elements with a transfer device, moving said transfer device, contacting said receiving surface of said substrate with said printable semiconductor elements disposed on said contact surface and separating said contact surface of said transfer device and said printable semiconductor elements are carried out using dry transfer printing.

7. The method of claim 1, wherein conformal contact is established between said contact surface having said printable semiconductor elements disposed thereon and said receiving surface of said substrate.

8. The method of claim 1, wherein said transfer device is a conformable transfer device.

9. The method of claim 1, wherein said bridge elements, said printable semiconductor elements and said mother wafer comprise a unitary structure.

10. The method of claim 1, wherein said bridge elements are connected to said printable semiconductor elements via an adhesive.

11. The method of claim 1, wherein said bridge elements are connected to said mother wafer via an adhesive.

12. The method of claim 1, wherein said bridge elements are connected to said printable semiconductor elements via an adhesive and wherein said bridge elements are connected to said mother wafer via an adhesive.

13. The method of claim 1, wherein a plurality of said bridge elements are connected to each of said printable semiconductor elements.

14. The method of claim 1, wherein each of said bridge elements has an average width selected from the range of 100 nanometers to 1000 microns, an average thickness selected from the range of 1 nanometers to 1000 microns and an average length selected from the range of 100 nanometers to 1000 microns.

15. The method of claim 1, wherein each of said bridge elements has an average width that is at least 2 times smaller than the average width of the printable semiconductor element to which it is connected.

16. The method of claim 1, wherein each of said bridge elements has an average width that is at least 10 times smaller than the average width of the printable semiconductor element to which it is connected.

17. The method of claim 1, wherein each of said bridge elements has an average thickness that is 1.5 times smaller than the average thickness of the printable semiconductor element to which it is connected.

18. The method of claim 1, wherein said printable semiconductor elements are functionalized to enhance said registered transfer to said transfer device.

19. The method of claim 1, wherein each of said printable semiconductor elements comprises a semiconductor ribbon extending a length along a principle longitudinal axis terminating in a first end and a second end, wherein said bridge element is connected to said first end and an additional bridge element is connected to said second end and to said mother wafer.

20. The method of claim 1 comprising a method of making an array of light emitting diodes or an array of solar cells.

21. The method of claim 1 comprising a method of making an array of diodes, an array of transistors or an integrated electronic circuit.

22. The method of claim 8, wherein said transfer device is an elastomeric stamp.

23. The method of claim 8, wherein said transfer device is a PDMS stamp.

24. The method of claim 18, wherein hydrophilic groups are added to the surfaces of the printable semiconductor elements or wherein the surfaces of the printable semiconductor elements are coated with a metal to enhance bonding to the contact surface of said transfer device.