Semiconductor device and structure
First Claim
Patent Images
1. A semiconductor device comprising:
- a first single crystal layer comprising first transistors and a first alignment mark;
at least one metal layer overlying said first single crystal layer, wherein said at least one metal layer comprises copper or aluminum; and
a second layer comprising activated dopant regions, said second layer overlying said at least one metal layer, wherein said second layer comprises second transistors, wherein said second transistors are processed aligned to said first alignment mark with less than 100 nm alignment error, wherein said second transistors comprise mono-crystal, horizontally-oriented transistors.
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Abstract
A semiconductor device including a first single crystal layer with first transistors and a first alignment mark; at least one metal layer overlying the first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer including activated dopant regions, the second layer overlying the at least one metal layer, wherein the second layer includes second transistors, wherein the second transistors are processed aligned to the first alignment mark with less than 100 nm alignment error, and the second transistors include mono-crystal, horizontally-oriented transistors.
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Citations
22 Claims
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1. A semiconductor device comprising:
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a first single crystal layer comprising first transistors and a first alignment mark; at least one metal layer overlying said first single crystal layer, wherein said at least one metal layer comprises copper or aluminum; and a second layer comprising activated dopant regions, said second layer overlying said at least one metal layer, wherein said second layer comprises second transistors, wherein said second transistors are processed aligned to said first alignment mark with less than 100 nm alignment error, wherein said second transistors comprise mono-crystal, horizontally-oriented transistors. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor device comprising:
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a first single crystal layer comprising first transistors, and a first alignment mark; at least one metal layer overlying said first single crystal layer, wherein said at least one metal layer comprises copper or aluminum; and a second layer comprising activated dopant regions, said second layer overlying said at least one metal layer, wherein said second layer comprises second transistors, wherein said second transistors are processed aligned to said first alignment mark with less than 100 nm alignment error, said second transistors forming a plurality of logic gates; wherein said second transistors are mono-crystal transistors. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A semiconductor device comprising:
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a first single crystal layer comprising first transistors and a first alignment mark; at least one metal layer overlying said first single crystal layer, wherein said at least one metal layer comprises copper or aluminum; a second layer overlying said at least one metal layer, wherein said second layer comprises a second alignment mark, second transistors, and a plurality of vias through said second layer, wherein said plurality of vias are aligned according to said first alignment mark and said second alignment mark; wherein said second transistors are mono-crystal transistors. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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Specification