Semiconductor device and method of forming the same

• US 8,395,197 B2
• Filed: 12/06/2010
• Issued: 03/12/2013
• Est. Priority Date: 12/15/2009
• Status: Expired due to Fees

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Nagai, Takeshi
• Primary Examiner(s): Blum, David S
• Application Number:
  US12/961,252
• Publication Number:
  US 20110140183A1
• Time in Patent Office: 827 Days
• Field of Search: 257/296, 257/345, 257/E27.016, 257/E29.255
• US Class Current: 257/296
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A semiconductor device includes a gate electrode on a gate insulating film over a semiconductor substrate, a first sidewall insulating film on a side surface of the gate electrode, and source and drain regions, each including a pocket diffusion layer of a first conductivity type, and first and second diffusion layers of a second conductivity type. The pocket diffusion layer is disposed in the semiconductor substrate. The first diffusion layer of a second conductivity type extends over the pocket diffusion layer. The first diffusion layer faces toward the gate electrode through the first sidewall insulating film. The second diffusion layer over the first diffusion layer is higher in impurity concentration than the first diffusion layer. The second diffusion layer is separated by the first diffusion layer from the pocket diffusion layer, and has a side surface which faces toward the first sidewall insulating film through the first diffusion layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a gate insulating film formed on a surface of the semiconductor substrate;

a gate electrode formed on the gate insulating film;

a first sidewall insulating film formed on a side surface of the gate electrode; and

source and drain regions, each of the source and drain regions comprising;

a pocket diffusion layer of a first conductivity type in the semiconductor device;

a first diffusion layer of a second conductivity type extending over the pocket diffusion layer, and the first diffusion layer facing toward the gate electrode through the first sidewall insulating film; and

a second diffusion layer of the second conductivity type being higher in impurity concentration than the first diffusion layer, the second diffusion layer extending over the first diffusion layer, the second diffusion layer being separated by the first diffusion layer from the pocket diffusion layer, the second diffusion layer having a side surface which faces toward the first sidewall insulating film through the first diffusion layer.

2. The semiconductor device according to claim 1, wherein the second diffusion layer has a bottom surface which is higher than the surface of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein the second diffusion layer has a bottom surface which is higher than the gate insulating film.

4. The semiconductor device according to claim 1, wherein the first diffusion layer contacts the pocket diffusion layer.

5. The semiconductor device according to claim 1, further comprising:

a second sidewall insulating film extending along the first sidewall insulating film, the second sidewall insulating film being positioned on a top portion of the first diffusion layer.

6. The semiconductor device according to claim 1, further comprising:

an isolation layer in the semiconductor substrate, the isolation layer defining an active region in which the source and drain regions are positioned, the isolation layer having a bottom surface which is deeper than a bottom surface of the pocket diffusion layer.

7. A semiconductor device comprising:

a first circuit region comprising a first transistor; and

a second circuit region comprising a second transistor, the second circuit region being isolated from the first circuit region,

the first transistor comprising;

a first active region;

a first gate insulating film formed on a surface of the first active region;

a first gate electrode formed on the first gate insulating film;

a first sidewall insulating film formed on a side surface of the first gate electrode; and

first source and drain regions, each of the first source and drain regions comprising;

a pocket diffusion layer of a first conductivity type in the first active region;

a first diffusion layer of a second conductivity type extending over the pocket diffusion layer, and the first diffusion layer facing toward the gate electrode through the first sidewall insulating film; and

a second diffusion layer of the second conductivity type being higher in impurity concentration than the first diffusion layer, the second diffusion layer extending over the first diffusion layer, the second diffusion layer being separated by the first diffusion layer from the pocket diffusion layer, the second diffusion layer having a side surface which faces toward the first sidewall insulating film through the first diffusion layer, and

the second transistor comprising;

a second active region;

a second gate electrode formed in the second active region;

a semiconductor layer on a surface of the second active region; and

second source and drain regions that formed in the semiconductor layer and in the second active region, and the second source and drain regions being lower in impurity concentration than the first diffusion layer.

8. The semiconductor device according to claim 7, wherein the second diffusion layer has a bottom surface which is higher than the surface of the semiconductor substrate.

9. The semiconductor device according to claim 7, wherein the second diffusion layer has a bottom surface which is higher than the gate insulating film.

10. The semiconductor device according to claim 7, wherein the first diffusion layer contacts the pocket diffusion layer.

11. The semiconductor device according to claim 7, further comprising:

a second sidewall insulating film extending along the first sidewall insulating film, the second sidewall insulating film being positioned on a top portion of the first diffusion layer.

12. The semiconductor device according to claim 7, wherein the first circuit region comprises a peripheral circuit region,

the second circuit region comprises a memory cell region,

the first transistor is a planer transistor,

the second transistor is a trench transistor, and

the second gate electrode is partially buried in the semiconductor substrate.

13. The semiconductor device according to claim 12, further comprising:

a bit line connected to a first one of the second source and drain regions in the memory cell region; and

a capacitor element connected to a second one of the second source and drain regions in the memory cell region.

14. A semiconductor device comprising:

a semiconductor substrate;

a gate insulating film on a surface of the semiconductor substrate;

a gate electrode on the gate insulating film;

a first sidewall insulating film on a side surface of the gate electrode;

a pocket diffusion layer of a first conductivity type in the semiconductor device;

a first diffusion layer of a second conductivity type facing toward the gate electrode through the first sidewall insulating film; and

a second diffusion layer of the second conductivity type being higher in impurity concentration than the first diffusion layer, the second diffusion layer having a side surface which faces toward the first sidewall insulating film through the first diffusion layer.

15. The semiconductor device according to claim 14, wherein the first diffusion layer comprises first and second portions, the first portion extends over the pocket diffusion layer, and the second portion extends along the first sidewall insulating film,

the second diffusion layer extends over the first portion of the first diffusion layer, the second diffusion layer is separated by the first portion of the first diffusion layer from the pocket diffusion layer, the second diffusion layer is separated by the second portion of the first diffusion layer and the first sidewall insulating film from the gate electrode.

16. The semiconductor device according to claim 14, wherein the second diffusion layer has a bottom surface which is higher than the surface of the semiconductor substrate.

17. The semiconductor device according to claim 14, wherein the first diffusion layer contacts the pocket diffusion layer.

18. The semiconductor device according to claim 14, further comprising:

a second sidewall insulating film extending along the first sidewall insulating film, the second sidewall insulating film being positioned on a top portion of the side surface of the second diffusion layer.

19. The semiconductor device according to claim 14, further comprising:

a bit line connected to the second diffusion layer.

20. The semiconductor device according to claim 14, further comprising:

a capacitor element connected to the second diffusion layer.