Semiconductor device and wafer with a test structure and method for assessing adhesion of under-bump metallization

• US 8,395,399 B2
• Filed: 12/01/2008
• Issued: 03/12/2013
• Est. Priority Date: 12/06/2007
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Rousseville, Lucie, Bardy, Serge, Le Duc, Philippe, Desmortreux, David
• Primary Examiner(s): Koval, Melissa
• Assistant Examiner(s): NGUYEN, TRUNG Q
• Application Number:
  US12/746,321
• Publication Number:
  US 20100253372A1
• Time in Patent Office: 1,562 Days
• Field of Search: 324/762.03, 324/762.05, 324/719, 324/765, 438/11, 438/18
• US Class Current: 324/705
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/70 Testing of connections between components and printed circuit boards G01R31/68 takes precedence
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Semiconductor device with a patterned pad metal layer and a patterned under-bump metallization layer being mutually electrically connected in a common contact area 22. The semiconductor device includes a first test structure 11 for determining a contact resistance between the patterned metallization layer and the patterned pad metal layer in the common contact areas 22. The first test structure includes a pad metal layer portion 24 and a metallization layer portion 18 being in electrical communication with the pad metal layer portion 24 through the common contact area 22. The first test structure 11 further includes connection areas 14, 16 that are electrically connected with each other substantially via the common contact area 22. Upon application of a current between the connection areas 14, 16 a voltage drop occurs that is representative for a voltage drop over the common contact area 22.

Claims

1. A semiconductor device having a patterned pad metal layer and a patterned under-bump metallization layer on said patterned pad metal layer and being mutually electrically connected therewith in a first common contact area, the semiconductor device comprising:

a first test structure for determining a contact resistance between the patterned metallization layer and the patterned pad metal layer in the first common contact area between the patterned metallization layer and the patterned pad metal layer, the first test structure including;

a pad metal layer portion being part of the patterned pad metal layer;

a first metallization layer portion being part of the patterned under-bump metallization layer and being electrically connected to the pad metal layer portion through the first common contact area, said metallization layer portion comprising a top surface including a first connection area defining a first external contact of the first test structure,

a second connection area defining a second external contact of the first test structure, said second connection area being comprised in the patterned metallization layer or the patterned pad metal layer outside the first common contact area, the first and second connection areas being electrically connected with each other via a first conductive path that extends through the metallization layer portion and the pad metal layer portion, via the first common contact area,

wherein the patterned under-bump metallization layer further comprises a second metallization portion and a third metallization portion, said pad metal layer portion being partially covered by and present below the first, second and third metallization portions, wherein;

the second contact area is formed on a top surface of the second metallization portion;

the first test structure further includes a third connection area formed on a top surface of the third metallization portion and a fourth connection area formed on the top surface of the first metallization portion;

the first conductive path comprises a first lead extending from the first connection area to the first common contact area and a second lead extending from the first common contact area to the second connection area, the first metallization layer portion comprising the first lead and the pad metal layer comprising the second lead;

said third and fourth connection areas are electrically connected with each other via a second conductive path comprising a third lead extending from the third connection area to the first common contact area and a fourth lead extending from the first common contact area to the fourth connection area, the pad metal layer comprising the third lead and the first metallization layer portion comprising the fourth lead, wherein the conductive coupling between the first conductive path and the second conductive path facilitates the measurement of a voltage drop between the third and fourth connection area that is representative for a voltage drop over the first common contact area upon the application of a current between the first and second connection area;

a second test structure having the same shape as the first test structure and having a second common contact area that is different in size from the first common contact area, wherein the first common contact area and the second common contact area have a similar shape in which dimensions of their planar geometry vary only by a numerical scale factor.

2. The semiconductor device according to claim 1, wherein a first imaginary straight line, positioned within the first common contact area, from the first lead connecting the first common contact area with the first connection area to the second lead connecting the second connection area with the first common contact area, has a length that is equal to a length of a second imaginary straight line of maximal length within the first common contact area.

3. The semiconductor device according to claim 1, wherein second common contact area is four times as large as the first common contact area.

4. A semiconductor wafer being provided with a semiconductor device according to claim 1.

5. A product including a semiconductor device according to claim 1.

12. The method according to claim 6, wherein the semiconductor wafer is a semiconductor wafer according to claim 4.

6. A method for assessing adhesion of a patterned under-bump metallization layer on a patterned pad metal layer of a semiconductor wafer, the method including electrically determining a contact resistance between a part of the patterned under-bump metallization layer and a part of the patterned pad metal layer, and examining whether the determined contact resistance exceeds a predetermined value, the electrically determining comprising:

determining a first resistance by applying a first known electrical current flowing between a first pair of connection areas defining respective external contacts through a first pad metal layer portion being the part of the patterned pad metal layer, through a first metallization layer portion being the part of the patterned under-bump metallization layer and comprising one of said first pair of connection areas on its top surface, and via a first common contact area between the first metallization layer portion and the first pad metal layer portion and measuring a first voltage over the first common contact area;

determining a second resistance in a similar way as determining the first resistance by applying a second known electrical current flowing between a third pair of connection areas defining respective external contacts through a second pad metal layer portion being part of the patterned pad metal layer, a second metallization layer portion being part of the patterned under-bump metallization layer and comprising one of said third pair of connection areas on its top surface, and a second common contact area between the second metallization layer portion and the second pad metal layer portion, the first common contact area and the second common contact area having a similar shape in which dimensions of their planar geometry vary only by a numerical scale factor;

measuring a second voltage over the second common contact area; and

determining the contact resistance from the first and the second resistance;

wherein a geometry of a conductive path between the first pair of connection areas via the first common contact area is different from a geometry of a conductive path between the third pair of connection areas via the second common contact area, so that an electrical layer resistance between the first pair of connection areas contributing to the first voltage is different from an electrical layer resistance between the third pair of connection areas contributing to the second voltage.

7. The method according to claim 6, wherein the first voltage is measured over a second pair of connection areas that is distinct from the first pair of connection areas and wherein the connection areas in said second pair are mutually connected through the first pad metal layer portion, the first metallization layer portion, and the first common contact area.

8. The method according to claim 6, wherein second common contact area is four times as large as the first common contact area.

9. The method according to claim 6, wherein the patterned under-bump metallization layer is deposited using electroless deposition.

10. The method according to claim 6, wherein the patterned pad metal layer is activated by an activation treatment.

11. The method according to claim 6, wherein the method includes conducting a shear test using a monitor wafer.