Switched capacitor voltage converters

• US 8,395,438 B2
• Filed: 06/26/2012
• Issued: 03/12/2013
• Est. Priority Date: 02/25/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dennard, Robert H., Ji, Brian L., Montoye, Robert K.
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US13/532,986
• Publication Number:
  US 20120262226A1
• Time in Patent Office: 259 Days
• Field of Search: 327/536, 363 59- 60
• US Class Current: 327/536
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

An on-chip voltage conversion apparatus for integrated circuits includes a first capacitor; a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain; a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain; a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.

Claims

1. An on-chip voltage conversion apparatus for integrated circuits, comprising:

a first capacitor;

a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain;

a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain;

a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and

a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain;

wherein actuating signals for the first NFET device and first PFET device are decoupled from one another such that the actuating signal for the first NFET device begins to transition from low to high after the actuating signal for the first PFET device begins to transition from low to high, and the actuating signal for the first PFET device begins to transition from high to low after he actuating signal for the first NFET device begins to transition from high to low; and

wherein actuating signals for the first NFET device and second PFET device are decoupled from one another such that the actuating signal for the second NFET device begins to transition from low to high after the actuating signal for the second PFET device begins to transition from low to high, and the actuating signal for the second PFET device begins to transition from high to low after he actuating signal for the second NFET device begins to transition from high to low.

2. The apparatus of claim 1, wherein the first capacitor comprises a deep trench capacitor.

3. The apparatus of claim 1, wherein the first and second NFET and PFET devices are formed on a silicon-on-insulator (SOI) substrate.

4. The apparatus of claim 1, wherein actuating signals to the first and second NFET and PFET devices are applied so as to charge and discharge the first capacitor between a first magnitude corresponding to the voltage difference across the first voltage domain and a second magnitude corresponding to the voltage difference across the second voltage domain.

5. The apparatus of claim 1, wherein for a down-conversion mode operation, the high side voltage rail of the second voltage domain, V2, is an input voltage and the high side voltage rail of the first voltage domain, V1, is an output voltage, such that V2>

2*V1.

6. The apparatus of claim 1, wherein for an up-conversion mode operation, the high side voltage rail of the first voltage domain, V1, is an input voltage and the high side voltage rail of the second voltage domain, V2, is an output voltage, such that V2<

2*V1.

7. The apparatus of claim 4, wherein the actuating signals to the first and second NFET and PFET devices are applied in a manner so as to prevent simultaneous conduction of any NFET device and any PFET device.

8. The apparatus of claim 4, wherein an output current is proportional to a switching frequency of the actuating signals.

9. The apparatus of claim 1, wherein:

gate terminals of the first NFET and PFET devices operate entirely within the first voltage domain; and

gate terminals of the second NFET and PFET devices operate entirely within the second voltage domain.

10. The apparatus of claim 1, wherein the first and second NFET and PFET devices are formed on bulk silicon substrates with triple well technology.

11. An on-chip voltage conversion system for integrated circuits, comprising:

a clock source having a plurality of clock phases;

a plurality of actuating signals corresponding to one of a plurality of phases; and

a plurality of voltage converters controlled by the actuating signals, with each voltage converter comprising;

a first capacitor;

a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain;

a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain;

a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and

a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain;

wherein actuating signals for the first NFET device and first PFET device are decoupled from one another such that the actuating signal for the first NFET device begins to transition from low to high after the actuating signal for the first PFET device begins to transition from low to high, and the actuating signal for the first PFET device begins to transition from high to low after he actuating signal for the first NFET device begins to transition from high to low; and

wherein actuating signals for the first NFET device and second PFET device are decoupled from one another such that the actuating signal for the second NFET device begins to transition from low to high after the actuating signal for the second PFET device begins to transition from low to high, and the actuating signal for the second PFET device begins to transition from high to low after he actuating signal for the second NFET device begins to transition from high to low.

12. A method of implementing on-chip voltage conversion for integrated circuits, the method comprising:

using a first NFET device to selectively couple a first electrode of a first capacitor to a low side voltage rail of a first voltage domain;

using a first PFET device to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain;

using a second NFET device to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and

using a second PFET device to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain;

wherein actuating signals for the first NFET device and first PFET device are decoupled from one another such that the actuating signal for the first NFET device begins to transition from low to high after the actuating signal for the first PFET device begins to transition from low to high, and the actuating signal for the first PFET device begins to transition from high to low after he actuating signal for the first NFET device begins to transition from high to low; and

wherein actuating signals for the first NFET device and second PFET device are decoupled from one another such that the actuating signal for the second NFET device begins to transition from low to high after the actuating signal for the second PFET device begins to transition from low to high, and the actuating signal for the second PFET device begins to transition from high to low after he actuating signal for the second NFET device begins to transition from high to low.

13. The method of claim 12, wherein the first capacitor comprises a deep trench capacitor.

14. The method of claim 13, wherein the first and second NFET and PFET devices are formed on a silicon-on-insulator (SOI) substrate.

15. The method of claim 12, further comprising applying actuating signals to the first and second NFET and PFET devices so as to charge and discharge the first capacitor between a first magnitude corresponding to the voltage difference across the first voltage domain and a second magnitude corresponding to the voltage difference across the second voltage domain.

16. The method of claim 15, wherein for a down-conversion mode operation, the voltage of the second voltage domain, V2, is an input voltage and the voltage of the first voltage domain, V1, is an output voltage, such that V2>

2*V1.

17. The method of claim 15, wherein for an up-conversion mode operation, the voltage of the first voltage domain, V1, is an input voltage and the voltage of the second voltage domain, V2, is an output voltage, such that V2<

2*V1.