Ring oscillator

• US 8,395,455 B1
• Filed: 10/14/2011
• Issued: 03/12/2013
• Est. Priority Date: 10/14/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Chien-Liang
• Primary Examiner(s): Johnson, Ryan
• Assistant Examiner(s): Rivera, Christian L
• Application Number:
  US13/274,181
• Time in Patent Office: 515 Days
• Field of Search: 331/57
• US Class Current: 331/57
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

A ring oscillator includes a plurality of inverting delay units serially connected in a form of a ring. Each of the inverting delay units receives an input signal and generates an output signal, and each of the inverting delay units includes a buffer and a delay circuit. The buffer has an input terminal and an output terminal. The input terminal receives the input signal, and the output terminal generates a buffered input signal. The delay circuit serves to provide a first time delay and a second time delay. Besides, according to a voltage level of the buffered input signal, the delay circuit provides a first reference voltage to generate the output signal after the first time delay or provides a second reference voltage to generate the output signal after the second time delay.

Claims

1. A ring oscillator having N inverting delay units serially connected in a form of a ring, each of the inverting delay units receiving an input signal and generating an output signal, N being a positive integer, each of the inverting delay units comprising:

a buffer having an input terminal and an output terminal, the input terminal receiving the input signal, the output terminal generating a buffered input signal; and

a delay circuit coupled to the output terminal of the buffer for providing a first time delay and a second time delay, the delay circuit providing a first reference voltage to generate the output signal after the first time delay or providing a second reference voltage to generate the output signal after the second time delay according to a voltage level of the buffered input signal, wherein the delay circuit comprises;

a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor receiving the first reference voltage, the control terminal of the first transistor receiving the buffered input signal;

a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor receiving the second reference voltage, the control terminal of the second transistor receiving the buffered input signal;

a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor receiving the buffered input signal, the control terminal of the third transistor being coupled to the second terminal of the first transistor, the second terminal of the third transistor generating the output signal; and

a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor receiving the buffered input signal, the control terminal of the fourth transistor being coupled to the second terminal of the second transistor, the second terminal of the fourth transistor being coupled to the second terminal of the third transistor.

2. The ring oscillator as recited in claim 1, wherein the delay circuit further comprises:

a fifth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor being coupled to the second terminal of the first transistor, the control terminal of the fifth transistor receiving the output signal, the second terminal of the fifth transistor generating an inverting output signal; and

a sixth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the sixth transistor being coupled to the second terminal of the second transistor, the control terminal of the sixth transistor receiving the output signal, the second terminal of the sixth transistor being coupled to the second terminal of the fifth transistor.

3. The ring oscillator as recited in claim 2, wherein the fifth transistor is a p-type transistor, the sixth transistor is an n-type transistor, the first reference voltage is a power source voltage, and the second reference voltage is a ground voltage.

4. The ring oscillator as recited in claim 2, wherein the fifth transistor is an n-type transistor, the sixth transistor is a p-type transistor, the first reference voltage is a ground voltage, and the second reference voltage is a power source voltage.

5. The ring oscillator as recited in claim 1, wherein the first and fourth transistors are p-type transistors, the second and third transistors are n-type transistors, the first reference voltage is a power source voltage, and the second reference voltage is a ground voltage.

6. The ring oscillator as recited in claim 1, wherein the first and fourth transistors are n-type transistors, the second and third transistors are p-type transistors, the second reference voltage is a power source voltage, and the first reference voltage is a ground voltage.

7. The ring oscillator as recited in claim 1, wherein the buffer is an inverter, and the buffered input signal is an inverted signal of the input signal.

8. The ring oscillator as recited in claim 1, wherein the first time delay is equal to a sum of a time frame during which the first transistor is turned on based on the buffered input signal, a time frame during which the third transistor receives the first reference voltage transmitted from the first transistor and is turned on, and a time frame during which the buffered input signal passes through the third transistor and becomes the output signal.

9. The ring oscillator as recited in claim 1, wherein the second time delay is equal to a sum of a time frame during which the second transistor is turned on based on the buffered input signal, a time frame during which the fourth transistor receives the second reference voltage transmitted from the second transistor and is turned on, and a time frame during which the buffered input signal passes through the fourth transistor and becomes the output signal.