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Variable phase amplifier circuit and method of use

  • US 8,395,456 B2
  • Filed: 03/16/2011
  • Issued: 03/12/2013
  • Est. Priority Date: 02/04/2009
  • Status: Active Grant
First Claim
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1. A variable phase amplifier circuit comprising:

  • a phase splitter circuit, wherein the phase splitter circuit generates a first and a second differential signal pair in response to receiving an input differential signal pair, and wherein;

    a phase of the second differential signal pair is shifted 90 degrees with respect to a phase of the first differential signal pair;

    a phase of a second end of the first differential signal pair is shifted 180 degrees with respect to a phase of a first end of the first differential signal pair;

    a phase of a second end of the second differential signal pair is shifted 180 degrees with respect to a phase of a first end of the second differential signal pair;

    a first variable gain amplifier circuit coupled to the phase splitter circuit, wherein the first variable gain amplifier circuit comprises;

    a first transistor, wherein the first transistor comprises;

    a first transistor emitter node, wherein the first transistor emitter node is coupled to an adjustable current source; and

    a first transistor collector node, wherein the first transistor collector node is coupled to a supply voltage through a first resistor, and wherein the first transistor collector node outputs the first end of the first scaled differential signal pair in response to the first transistor base node receiving the first end of the first differential signal pair; and

    a second transistor, wherein the second transistor comprises;

    a second transistor emitter node, wherein the second transistor emitter node is coupled to the first transistor emitter node; and

    a second transistor collector node, wherein the second transistor collector node is coupled to the supply voltage through a second resistor, and wherein the second transistor collector node outputs the second end of the first scaled differential signal pair in response to the second transistor base node receiving the second end of the first differential signal pair;

    wherein the first variable gain amplifier circuit scales the first differential signal pair by a first scale factor in response to receiving the first differential signal pair;

    a second variable gain amplifier circuit coupled to the phase splitter circuit, wherein the second variable gain amplifier circuit scales the second differential signal pair by a second scale factor in response to receiving the second differential signal pair; and

    a summation circuit coupled to the first and the second variable gain amplifier circuits, wherein the summation circuit receives a first and a second scaled differential signal pair from the first and the second variable gain amplifier circuits respectively, and outputs a modified differential signal pair in response;

    wherein a phase of the modified differential signal pair is a function of the first scale factor, andwherein the summation circuit sums a first end of the first scaled differential signal pair to a first end of the second scaled differential signal pair, andwherein the summation circuit sums a second end of the first scaled differential signal pair to a second end of the second scaled differential signal pair.

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