Subset selection of RFID tags using light
First Claim
1. A circuit to provide a power supply, comprising:
- a first bias circuit to supply a gate to source bias, which is independent of a direct current (DC) output voltage;
a voltage multiplier circuit coupled to the first bias circuit, the voltage multiplier circuit having at least one n-channel metal-oxide-semiconductor (NMOS) transistor with the voltage multiplier circuit to generate the DC output voltage for powering a RF identification tag, the first bias circuit to receive a RF input source and generate the gate to source bias for a gate terminal of the NMOS transistor.
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Accused Products
Abstract
Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.
31 Citations
20 Claims
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1. A circuit to provide a power supply, comprising:
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a first bias circuit to supply a gate to source bias, which is independent of a direct current (DC) output voltage; a voltage multiplier circuit coupled to the first bias circuit, the voltage multiplier circuit having at least one n-channel metal-oxide-semiconductor (NMOS) transistor with the voltage multiplier circuit to generate the DC output voltage for powering a RF identification tag, the first bias circuit to receive a RF input source and generate the gate to source bias for a gate terminal of the NMOS transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A multi-stage voltage multiplier circuit, comprising:
a first stage of the multi-stage voltage multiplier circuit comprising; a first bias circuit having no effective load; a first voltage multiplier circuit coupled to the first bias circuit, the first voltage multiplier circuit having at least one n-channel metal-oxide-semiconductor (NMOS) transistor with the first voltage multiplier circuit to generate a direct current (DC) output voltage, the first bias circuit to receive a RF input source and generate a gate to source bias for a gate terminal of the NMOS transistor of the first voltage multiplier circuit. - View Dependent Claims (9, 10, 11, 12)
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13. A demodulator circuit, comprising:
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a first bias circuit to supply a gate to source bias; a first clamping transistor coupled to the first bias circuit; and a voltage multiplier circuit coupled to the clamping transistor, the voltage multiplier circuit having at least one n-channel metal-oxide-semiconductor (NMOS) transistor with the voltage multiplier circuit to generate a demodulated output signal that demodulates information carried by a RF input signal, the first bias circuit to receive the RF input signal and generate the gate to source bias for a gate terminal of the NMOS transistor, the first clamping transistor to limit a value of the gate to source bias to approximately one threshold voltage of the first clamping transistor or less. - View Dependent Claims (14, 15, 16, 17)
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18. A circuit to provide a power supply, comprising:
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a first bias circuit to supply a gate to source bias, which is independent of a direct current (DC) output voltage; and a voltage multiplier circuit coupled to the first bias circuit, the voltage multiplier circuit having at least one p-channel metal-oxide-semiconductor (PMOS) transistor with the voltage multiplier circuit to generate the DC output voltage for powering a RF identification tag, the first bias circuit to receive a RF input source and generate the gate to source bias for a gate terminal of the PMOS transistor. - View Dependent Claims (19, 20)
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Specification