High speed resistor-DAC for SAR DAC

• US 8,395,538 B2
• Filed: 06/20/2011
• Issued: 03/12/2013
• Est. Priority Date: 06/20/2011
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Nagaraj, Krishnasawamy, Park, Joonsung, Das, Abhijit Kurmar
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US13/164,478
• Publication Number:
  US 20120319886A1
• Time in Patent Office: 631 Days
• Field of Search: 341/144, 341/155, 341/156, 341/163, 341/172
• US Class Current: 341/163
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• CPC Class Codes: H03M 1/765 using a single level of switches which are controlled by unary decoded digital signals
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

A singled-ended, successive approximation register analog-to-digital converter convert an analog input voltage to a digital representation comprising m upper order bits and a number of lower order bits. The SAR ADC comprises SAR logic, a resistive network, multiple switches, and first and second LSB capacitors. The switches also comprises two sets of switches coupled to the resistive network, each set of switches is configured to couple a selected tap to each of the first and second LSB capacitors. When determining the lower order bits, the SAR logic is configured to control the sets of switches to change the first and second taps from one cycle in which one of the lower order bits is determined to a next cycle in which the next of the lower order bits is determined so that the voltage of both taps changes by a decreasing amount with each succeeding bit being determined.

Claims

1. A singled-ended, successive approximation register (SAR) analog-to-digital converter (ADC) configured to convert an analog input voltage to a digital representation comprising m upper order bits and a number of lower order bits, comprising:

SAR logic;

a resistive network;

a plurality of switches individually controlled by said SAR logic;

a plurality of most significant bit (MSB) capacitors, some of which are connected to a static voltage; and

a pair of least significant bit (LSB) capacitors, a first LSB capacitor connected to one of the switches that selectively couples said first LSB capacitor to a reference voltage (Vref) or a selected first tap in said resistive network, and a second LSB capacitor connected to one of the switches that selectively couples said second LSB capacitor to the analog input voltage or a selected second tap in said resistive network;

wherein said plurality of switches also comprises two sets of switches coupled to said resistive network, each set of switches is configured to couple a selected tap to each of said first and second LSB capacitors; and

wherein, when determining the lower order bits, said SAR logic is configured to control the sets of switches to change the first and second taps from one cycle in which one of the lower order bits is determined to a next cycle in which the next of the lower order bits is determined so that the voltage of the first and second taps changes by Vref/[2<sup>(n−

m+1)</sup>] where n is the nth bit being determined.

2. The SAR ADC of claim 1, wherein the voltage change of the first tap is in a direction opposite that of the voltage change of the second tap.

3. The SAR ADC of claim 1 wherein the direction of change of the voltage of each tap is a function of the preceding determined bit.

4. The SAR ADC of claim 1 wherein each of at least some of said MSB capacitors is connected to a switch that connects to the analog input voltage, Vref, and ground.

5. A singled-ended, successive approximation register (SAR) analog-to-digital converter (ADC) configured to convert an analog input voltage to a digital representation comprising m upper order bits and a number of lower order bits, comprising:

SAR logic

a resistive network;

a plurality of switches individually controlled by said SAR logic; and

a pair of least significant bit (LSB) capacitors, a first LSB capacitor connected to one of the switches that selectively couples said first LSB capacitor to a reference voltage (Vref) or a selected first tap in said resistive network, and a second LSB capacitor connected to one of the switches that selectively couples said second LSB capacitor to the analog input voltage or a selected second tap in said resistive network;

wherein said plurality of switches also comprises two sets of switches coupled to said resistive network, each set of switches is configured to couple a selected tap to each of said first and second LSB capacitors; and

wherein, when determining the lower order bits, said SAR logic is configured to control the sets of switches to change the first and second taps from one cycle in which one of the lower order bits is determined to a next cycle in which the next of the lower order bits is determined so that the voltage of both the first and second taps changes by a decreasing amount with each succeeding bit being determined.

6. The SAR ADC of claim 5 wherein the amount of the voltage change with each succeeding lower order bit is Vref/[2⁽ⁿ⁻

m+1)] where n is the nth bit being determined.

7. The SAR ADC of claim 5, wherein the voltage change of the first tap is in a direction opposite that of the voltage change of the second tap.

8. The SAR ADC of claim 5 wherein the direction of change of the voltage of each tap is a function of the preceding determined bit.

9. The SAR ADC of claim 5 further comprising a plurality of most significant bit (MSB) capacitors, some of which are connected to a static voltage.

10. The SAR ADC of claim 5 wherein the change in voltage on the taps depends on value of the preceding bit.