Semiconductor memory device and driving method thereof

• US 8,395,931 B2
• Filed: 01/19/2011
• Issued: 03/12/2013
• Est. Priority Date: 01/22/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Takemura, Yasuhiko
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US13/009,034
• Publication Number:
  US 20110182110A1
• Time in Patent Office: 783 Days
• Field of Search: 365/102
• US Class Current: 365/149
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A semiconductor device which stores data by using a transistor whose leakage current between source and drain in an off state is small as a writing transistor. In a matrix including a plurality of memory cells in which a drain of the writing transistor is connected to a gate of a reading transistor and the drain of the writing transistor is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line; a source of the writing transistor is connected to a writing bit line; and a source and a drain of the reading transistor are connected to a reading bit line and a bias line. In order to reduce the number of wirings, the writing bit line or the bias line is substituted for the reading bit line in another column.

Claims

1. A semiconductor memory device comprising:

a first line;

a second line;

a third line;

a fourth line;

a fifth line; and

a memory cell comprising;

a first transistor;

a second transistor; and

a capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one of electrodes of the capacitor,

wherein a gate of the first transistor is electrically connected to the first line,

wherein the other of the source and the drain of the first transistor is electrically connected to the fifth line,

wherein one of a source and a drain of the second transistor is electrically connected to the third line,

wherein the other of the source and the drain of the second transistor is electrically connected to the fourth line,

wherein the other of electrodes of the capacitor is electrically connected to the second line,

wherein the first transistor comprises a semiconductor layer including an oxide semiconductor, and

wherein an area of the capacitor is less than 2 times an area of a channel region of the second transistor.

2. The semiconductor memory device according to claim 1, wherein a width of the second line is greater than or equal to 0.5 times and less than or equal to 1.5 times a channel width of the first transistor.

3. The semiconductor memory device according to claim 1, wherein leakage current between the source and the drain of the first transistor in an off state is 1×

10<sup>−

20</sup> A or smaller at a temperature of 25°

C.

4. The semiconductor memory device according to claim 1, wherein carrier concentration of the oxide semiconductor is less than 1×

10¹⁴ cm<sup>−

3</sup>.

5. A semiconductor memory device comprising:

a first line;

a second line;

a third line;

a fourth line; and

a memory cell comprising;

first transistor;

a second transistor; and

a capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one of electrodes of the capacitor,

wherein a gate of the first transistor is electrically connected to the first line,

wherein the other of the source and the drain of the first transistor is electrically connected to the third line,

wherein one of a source and a drain of the second transistor is electrically connected to the third line,

wherein the other of the source and the drain of the second transistor is electrically connected to the fourth line,

wherein the other of electrodes of the capacitor is electrically connected to the second line,

wherein the first transistor comprises a semiconductor layer including an oxide semiconductor, and

wherein an area of the capacitor is less than 2 times an area of a channel region of the second transistor.

6. The semiconductor memory device according to claim 5, wherein a width of the second line is greater than or equal to 0.5 times and less than or equal to 1.5 times a channel width of the first transistor.

7. The semiconductor memory device according to claim 5, wherein leakage current between the source and the drain of the first transistor in an off state is 1×

10<sup>−

20</sup> A or smaller at a temperature of 25°

C.

8. The semiconductor memory device according to claim 5, wherein carrier concentration of the oxide semiconductor is less than 1×

10¹⁴ cm<sup>−

3</sup>.

9. A semiconductor memory device comprising:

a first line;

a second line;

a third line;

a fourth line;

a fifth line;

a sixth line;

a first memory cell including a first transistor, a second transistor, and a first capacitor; and

a second memory cell including a third transistor, a fourth transistor, and a second capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one of electrodes of the first capacitor,

wherein a gate of the first transistor is electrically connected to the first line,

wherein the other of the source and the drain of the first transistor is electrically connected to the fifth line,

wherein one of a source and a drain of the second transistor is electrically connected to the third line,

wherein the other of the source and the drain of the second transistor is electrically connected to the fourth line,

wherein the other of electrodes of the first capacitor is electrically connected to the second line,

wherein the first transistor comprises a first semiconductor layer including an oxide semiconductor,

wherein an area of the first capacitor is less than 2 times an area of a channel region of the second transistor,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor and one of electrodes of the second capacitor,

wherein a gate of the third transistor is electrically connected to the first line,

wherein the other of the source and the drain of the third transistor is electrically connected to the sixth line,

wherein one of a source and a drain of the fourth transistor is electrically connected to the third line,

wherein the other of electrodes of the second capacitor is electrically connected to the second line,

wherein the third transistor comprises a second semiconductor layer including the oxide semiconductor,

wherein an area of the second capacitor is less than 2 times an area of a channel region of the fourth transistor.

10. The semiconductor memory device according to claim 9,

wherein a width of the second line is greater than or equal to 0.5 times and less than or equal to 1.5 times a channel width of the first transistor and the third transistor.

11. The semiconductor memory device according to claim 9,

wherein leakage current between the source and the drain of the first transistor is 1×

10<sup>−

20</sup> A or smaller at a temperature of 25°

C., and

wherein leakage current between the source and the drain of the third transistor is 1×

10<sup>−

20</sup> A or smaller at a temperature of 25°

C.

12. The semiconductor memory device according to claim 9, wherein each carrier concentration of the oxide semiconductor of the first transistor and the third transistor is less than 1×

10¹⁴ cm<sup>−

3</sup>.

13. A driving method of a semiconductor memory device comprising:

a first line;

a second line; and

a memory cell including a first transistor, a second transistor, and a capacitor, wherein the first transistor comprises a semiconductor layer including an oxide semiconductor, wherein one of a source and a drain of the first transistor is electrically connected to the first line, wherein the other of the source and the drain of the first transistor is electrically connected to the capacitor and a gate of the second transistor, wherein one of a source and a drain of the second transistor is electrically connected to the first line, and wherein the other of the source and the drain of the second transistor is electrically connected to the second line,

the driving method comprising the steps of;

turning on the first transistor;

supplying a first potential to the gate of the second transistor and the capacitor through the first line and the first transistor;

supplying a second potential to the second line; and

holding the first potential in the gate of the second transistor and the capacitor by turning off the first transistor,

wherein the step of supplying the first potential is performed at the same time as the step of supplying the second potential, and

wherein a level of the first potential is the same as a level of the second potential.

14. The driving method of a semiconductor memory device according to claim 13, wherein an area of the capacitor is less than 2 times an area of a channel region of the second transistor.

15. The driving method of a semiconductor memory device according to claim 13, wherein leakage current between the source and the drain of the first transistor in an off state is 1×

10<sup>−

20</sup> A or smaller at a temperature of 25°

C.

16. The driving method of a semiconductor memory device according to claim 13, wherein carrier concentration of the oxide semiconductor is less than 1×

10¹⁴ cm<sup>−

3</sup>.

17. A driving method of a semiconductor memory device comprising:

a first line;

a second line;

a first memory cell including a first transistor, a second transistor, and a first capacitor, wherein the first transistor comprises a first semiconductor layer including an oxide semiconductor, wherein one of a source and a drain of the first transistor is electrically connected to the first line, wherein the other of the source and the drain of the first transistor is electrically connected to one of electrodes of the first capacitor and a gate of the second transistor, wherein the other of the electrodes of the first capacitor is electrically connected to the second line, and wherein one of a source and a drain of the second transistor is electrically connected to the first line; and

a second memory cell including a third transistor, a fourth transistor, and a second capacitor, wherein the third transistor comprises a second semiconductor layer including the oxide semiconductor, wherein one of a source and a drain of the third transistor is electrically connected to the first line, wherein the other of the source and the drain of the third transistor is electrically connected to one of electrodes of the second capacitor and a gate of the fourth transistor,

the driving method comprising the steps of;

turning on the first transistor;

supplying a first potential to the gate of the second transistor and the first capacitor through the first line and the first transistor;

holding the first potential in the gate of the second transistor and the first capacitor by turning off the first transistor;

turning on the third transistor;

holding a potential of the second line at a second potential so that the second transistor is kept off regardless of a level of the first potential in the gate of the second transistor and the first capacitor,

supplying a third potential to the gate of the fourth transistor and the second capacitor through the first line and the third transistor while holding the potential of the second line at the second potential, and

holding the third potential in the gate of the fourth transistor and the second capacitor by turning off the third transistor.

18. The driving method of a semiconductor memory device according to claim 17,

wherein an area of the first capacitor is less than 2 times an area of a channel region of the second transistor, and

wherein an area of the second capacitor is less than 2 times an area of a channel region of the fourth transistor.

19. The driving method of a semiconductor memory device according to claim 17,

wherein leakage current between the source and the drain of the first transistor in an off state is 1×

10<sup>−

20</sup> A or smaller at a temperature of 25°

C., and

wherein leakage current between the source and the drain of the third transistor in an off state is 1×

10<sup>−

20</sup> A or smaller at a temperature of 25°

C.

20. The driving method of a semiconductor memory device according to claim 17, wherein each carrier concentration of the oxide semiconductor of the first transistor and the third transistor is less than 1×

10¹⁴ cm<sup>−

3</sup>.

21. A driving method of a semiconductor memory device comprising:

a first line;

a second line;

a first memory cell including a first transistor, a second transistor, and a capacitor, wherein the first transistor comprises a semiconductor layer including an oxide semiconductor, wherein one of a source and a drain of the first transistor is electrically connected to the first line, wherein the other of the source and the drain of the first transistor is electrically connected to the capacitor and a gate of the second transistor, wherein one of a source and a drain of the second transistor is electrically connected to the first line, and wherein the other of the source and the drain of the second transistor is electrically connected to the second line; and

a third transistor, wherein one of a source and a drain of the third transistor is electrically connected to the first line, and wherein the other of the source and the drain of the third transistor is electrically connected to the second line,

the driving method comprising the steps of;

turning on the third transistor;

turning on the first transistor;

supplying a potential to the gate of the second transistor and to the second line through the first line while the third transistor is in an on state, and

holding the potential by turning off the first transistor.

22. The driving method of a semiconductor memory device according to claim 21, wherein an area of the capacitor is less than 2 times an area of a channel region of the second transistor.

23. The driving method of a semiconductor memory device according to claim 21,

wherein leakage current between the source and the drain of the first transistor in an off state is 1×

10<sup>−

20</sup> A or smaller at a temperature of 25°

C., and

wherein leakage current between the source and the drain of the third transistor in an off state is 1×

10<sup>−

20</sup> A or smaller at a temperature of 25°

C.

24. The driving method of a semiconductor memory device according to claim 21, wherein carrier concentration of the oxide semiconductor is less than 1×

10¹⁴ cm<sup>−

3</sup>.