Memory controller
First Claim
1. A memory controller component that generates a timing signal, the memory controller component to control a dynamic random access memory component (DRAM), the memory controller component comprising:
- transmit circuitry to transmit, to the DRAM;
write data to be sampled by the DRAM on one or more edges of the timing signal, the timing signal requiring a first time interval to propagate from the memory controller component to the DRAM;
a first clock signal that requires a second time interval to propagate from the memory controller component to the DRAM; and
a write command to be sampled by the DRAM on one or more edges of the first clock signal, the write command associated with the write data; and
adjusting circuitry to control transmit timing within the transmit circuitry, the adjusting circuitry to adjust transmit timing of the write data and timing of the timing signal based on a difference between the first and second time intervals such that a rising edge of the timing signal at the DRAM is aligned with a rising edge of the first clock signal at the DRAM.
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Accused Products
Abstract
A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal.
288 Citations
38 Claims
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1. A memory controller component that generates a timing signal, the memory controller component to control a dynamic random access memory component (DRAM), the memory controller component comprising:
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transmit circuitry to transmit, to the DRAM; write data to be sampled by the DRAM on one or more edges of the timing signal, the timing signal requiring a first time interval to propagate from the memory controller component to the DRAM; a first clock signal that requires a second time interval to propagate from the memory controller component to the DRAM; and a write command to be sampled by the DRAM on one or more edges of the first clock signal, the write command associated with the write data; and adjusting circuitry to control transmit timing within the transmit circuitry, the adjusting circuitry to adjust transmit timing of the write data and timing of the timing signal based on a difference between the first and second time intervals such that a rising edge of the timing signal at the DRAM is aligned with a rising edge of the first clock signal at the DRAM. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A memory controller component that generates a first timing signal and second timing signal, the memory controller for controlling a first dynamic random access memory component (DRAM) and a second DRAM, the memory controller component comprising:
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transmit circuitry to transmit; a first clock signal to the first DRAM and second DRAM, the first clock signal requiring a first time interval to propagate from the memory controller component to the first DRAM and a second time interval to propagate from the memory controller component to the second DRAM, wherein the second time interval is longer than the first time interval; first write data to the first DRAM but not the second DRAM, the first write data to be sampled by the first DRAM on one or more edges of the first timing signal, the first timing signal requiring a third time interval to propagate from the memory controller component to the first DRAM; second write data to the second DRAM but not the first DRAM, the second write data to be sampled by the second DRAM on one or more edges of the second timing signal, the second timing signal requiring a fourth time interval to propagate from the memory controller component to the second DRAM; and a write command to the first DRAM and second DRAM, the write command to be sampled by the first DRAM and second DRAM on one or more edges of the first clock signal and the write command indicating that the first write data is to be stored within the first DRAM and the second write data is to be stored within the second DRAM; and adjusting circuitry to control transmit timing within the transmit circuitry, the adjusting circuitry to adjust (i) transmit timing of the first write data and timing of the first timing signal based on a difference between the first and third time intervals such that a rising edge of the first timing signal at the first DRAM is aligned with a first rising edge of the first clock signal at the first DRAM, and (ii) transmit timing of the second write data and timing of the second timing signal based on a difference between the second and fourth time intervals such that a rising edge of the second timing signal at the second DRAM is aligned with a second rising edge of the first clock signal at the second DRAM. - View Dependent Claims (19, 20, 21, 22, 23, 24)
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25. A memory controller component for controlling a dynamic random access memory (DRAM), the memory controller component comprising:
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a first transmitter circuit to transmit a first clock signal to the DRAM, wherein the first clock signal requires a first time interval to propagate from the memory controller component to the DRAM; a second transmitter circuit to transmit a write command to the DRAM to indicate that write data is to be stored within the DRAM, wherein the write command is sampled by the DRAM on one or more edges of the first clock signal; and a third transmitter circuit to transmit the write data to the DRAM, wherein the write data is sampled by the DRAM on one or more edges of a timing signal, wherein the timing signal requires a second time interval to propagate from the memory controller component to the DRAM; and adjusting circuitry to adjust transmit timing of the write data and timing of the timing signal based on a difference between the first and second time intervals such that a rising edge of the timing signal is aligned with a rising edge of the first clock signal at the DRAM. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33)
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34. A memory controller component for controlling a first dynamic random access memory (DRAM) and a second DRAM, the memory controller component comprising:
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a first transmitter circuit to transmit a first clock signal to the first DRAM and second DRAM, wherein the first clock signal requires a first time interval to propagate from the memory controller component to the first DRAM and a second time interval to propagate from the memory controller component to the second DRAM, the second time interval being greater than the first time interval; a second transmitter circuit to transmit a write command to the first DRAM and second DRAM to indicate that first write data is to be stored within the first DRAM and second write data is to be stored within the second DRAM, wherein the write command is sampled by the first DRAM and second DRAM on one or more edges of the first clock signal; a third transmitter circuit to transmit the first write data to the first DRAM but not the second DRAM, wherein the first write data is sampled by the first DRAM on one or more edges of a first timing signal, wherein the first timing signal requires a third time interval, different from the first time interval, to propagate on a first timing signal wire from the memory controller component to the first DRAM; a fourth transmitter circuit to transmit the second write data to the second DRAM but not the first DRAM, wherein the second write data is sampled by the second DRAM on one or more edges of a second timing signal, wherein the second timing signal requires a fourth time interval, different from the second time interval, to propagate on a second timing signal wire from the memory controller component to the second DRAM; and an adjusting circuit to align a rising edge of the first timing signal with a first rising edge of the first clock signal at the first DRAM by adjusting timing of the first timing signal based on the difference between the first time interval and third time interval, and to align a rising edge of the second timing signal with a second rising edge of the first clock signal at the second DRAM by adjusting timing of the second timing signal based on the difference between the second time interval and fourth time interval. - View Dependent Claims (35, 36, 37, 38)
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Specification