Memory controller

• US 8,395,951 B2
• Filed: 05/02/2012
• Issued: 03/12/2013
• Est. Priority Date: 04/24/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Tsern, Ely K., Perego, Richard E., Hampel, Craig E.
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US13/461,923
• Publication Number:
  US 20120213020A1
• Time in Patent Office: 314 Days
• Field of Search: 365/194, 365/191, 365/189.011, 365/189.16
• US Class Current: 365/194
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal.

Claims

1. A memory controller component that generates a timing signal, the memory controller component to control a dynamic random access memory component (DRAM), the memory controller component comprising:

transmit circuitry to transmit, to the DRAM;

write data to be sampled by the DRAM on one or more edges of the timing signal, the timing signal requiring a first time interval to propagate from the memory controller component to the DRAM;

a first clock signal that requires a second time interval to propagate from the memory controller component to the DRAM; and

a write command to be sampled by the DRAM on one or more edges of the first clock signal, the write command associated with the write data; and

adjusting circuitry to control transmit timing within the transmit circuitry, the adjusting circuitry to adjust transmit timing of the write data and timing of the timing signal based on a difference between the first and second time intervals such that a rising edge of the timing signal at the DRAM is aligned with a rising edge of the first clock signal at the DRAM.

2. The memory controller component of claim 1, wherein the write data accompanies the timing signal while the write data and the timing signal propagate from the memory controller component to the DRAM.

3. The memory controller component of claim 1, wherein the timing signal is a strobe signal.

4. The memory controller component of claim 1, wherein the timing signal is a second clock signal.

5. The memory controller component of claim 1, wherein the transmit timing of the write data is adjusted by an amount that increases a signaling margin of the write data being sampled by the DRAM.

6. The memory controller component of claim 1, wherein the adjusting circuitry comprises circuitry to adjust a phase of a transmit clock signal that times transmission of the write data.

7. The memory controller component of claim 1, wherein the rising edge of the timing signal is aligned with the rising edge of the first clock signal to enable the DRAM to receive both the write data and the write command in a single clock domain.

8. The memory controller component of claim 1, wherein the rising edge of the timing signal is aligned with the rising edge of the first clock signal by adjusting timing of the timing signal such that the timing signal and the first clock signal transition from a low state to a high state at substantially the same time at respective timing signal inputs of the DRAM.

9. The memory controller component of claim 1, wherein the adjusting circuitry comprises clock generation circuitry to generate a plurality of phase-distributed clock signals and an internal clock signal, the plurality of phase-distributed clock signals having phase offsets that are substantially evenly distributed within a cycle time of the internal clock signal, wherein the memory controller adjusts the transmit timing of the write data using clock signals selected from the plurality of phase-distributed clock signals.

10. The memory controller of claim 9, wherein the clock generation circuitry comprises a phase-locked loop circuit to generate the internal clock signal based on a reference clock signal that has a lower frequency than the internal clock signal.

11. The memory controller component of claim 9, wherein the adjusting circuitry further comprises a plurality of phase offset selection circuits, and wherein a phase offset selection circuit of the plurality of phase offset selection circuits selects a phase-distributed clock signal from the plurality of phase-distributed clock signals to be a timing reference for transmission of the write data.

12. The memory controller of component of claim 11, wherein the phase offset selection circuit comprises a multiplexer to select the phase-distributed clock signal.

13. The memory controller component of claim 11, wherein the phase offset selection circuit comprises a phase interpolator to select the phase-distributed clock signal.

14. The memory controller component of claim 1, wherein the timing signal is transmitted such that the propagation of the timing signal from the memory controller component to the DRAM tracks propagation of the write data from the memory controller component to the DRAM.

15. The memory controller component of claim 1, wherein the first clock signal is transmitted such that the propagation of the first clock signal from the memory controller component to the DRAM via a first signal path tracks propagation of the write command from the memory controller component to the DRAM via a second signal path.

16. The memory controller component of claim 1, wherein the first clock signal is provided to the memory controller component from an external clock signal generator circuit.

17. The memory controller component of claim 1, wherein the transmit circuitry comprises:

a first transmitter circuit to transmit the first clock signal; and

a second transmitter circuit to transmit the write command, wherein transmission of the write command is timed using the first clock signal.

18. A memory controller component that generates a first timing signal and second timing signal, the memory controller for controlling a first dynamic random access memory component (DRAM) and a second DRAM, the memory controller component comprising:

transmit circuitry to transmit;

a first clock signal to the first DRAM and second DRAM, the first clock signal requiring a first time interval to propagate from the memory controller component to the first DRAM and a second time interval to propagate from the memory controller component to the second DRAM, wherein the second time interval is longer than the first time interval;

first write data to the first DRAM but not the second DRAM, the first write data to be sampled by the first DRAM on one or more edges of the first timing signal, the first timing signal requiring a third time interval to propagate from the memory controller component to the first DRAM;

second write data to the second DRAM but not the first DRAM, the second write data to be sampled by the second DRAM on one or more edges of the second timing signal, the second timing signal requiring a fourth time interval to propagate from the memory controller component to the second DRAM; and

a write command to the first DRAM and second DRAM, the write command to be sampled by the first DRAM and second DRAM on one or more edges of the first clock signal and the write command indicating that the first write data is to be stored within the first DRAM and the second write data is to be stored within the second DRAM; and

adjusting circuitry to control transmit timing within the transmit circuitry, the adjusting circuitry to adjust (i) transmit timing of the first write data and timing of the first timing signal based on a difference between the first and third time intervals such that a rising edge of the first timing signal at the first DRAM is aligned with a first rising edge of the first clock signal at the first DRAM, and (ii) transmit timing of the second write data and timing of the second timing signal based on a difference between the second and fourth time intervals such that a rising edge of the second timing signal at the second DRAM is aligned with a second rising edge of the first clock signal at the second DRAM.

19. The memory controller component of claim 18 wherein the first write data accompanies the first timing signal while the first write data and the first timing signal propagate from the memory controller component to the first DRAM, and the second write data accompanies the second timing signal while the second write data and the second timing signal propagate from the memory controller component to the second DRAM.

20. The memory controller component of claim 18, wherein the write command and the first clock signal are transmitted to the first and second DRAMs via respective sets of one or more signal lines, wherein each signal line of the respective sets of one or more signal lines is coupled to the first and second DRAMs at different points along its length such that the first clock signal and write command propagate from the memory controller component past the first DRAM to the second DRAM, wherein the first clock signal arrives at the first DRAM before arriving at any other DRAM and the write command arrives at the first DRAM before arriving at any other DRAM.

21. The memory controller component of claim 18, wherein the first rising edge of the first clock signal is the same edge as the second rising edge of the first clock signal.

22. The memory controller component of claim 18, wherein the first timing signal and second timing signal are strobe signals.

23. The memory controller component of claim 18, wherein the first timing signal and second timing signal are a second clock signal and third clock signal, respectively.

24. The memory controller component of claim 18, wherein the transmit timings of the first write data and second write data are adjusted by amounts that increase the signaling margin when the first write data and second write data are respectively sampled by the first DRAM and second DRAM.

25. A memory controller component for controlling a dynamic random access memory (DRAM), the memory controller component comprising:

a first transmitter circuit to transmit a first clock signal to the DRAM, wherein the first clock signal requires a first time interval to propagate from the memory controller component to the DRAM;

a second transmitter circuit to transmit a write command to the DRAM to indicate that write data is to be stored within the DRAM, wherein the write command is sampled by the DRAM on one or more edges of the first clock signal; and

a third transmitter circuit to transmit the write data to the DRAM, wherein the write data is sampled by the DRAM on one or more edges of a timing signal, wherein the timing signal requires a second time interval to propagate from the memory controller component to the DRAM; and

adjusting circuitry to adjust transmit timing of the write data and timing of the timing signal based on a difference between the first and second time intervals such that a rising edge of the timing signal is aligned with a rising edge of the first clock signal at the DRAM.

26. The memory controller component of claim 25, wherein the write data accompanies the timing signal while the write data and timing signal propagate from the memory controller component to the DRAM.

27. The memory controller component of claim 25, wherein the transmit timing of the write data is adjusted by an amount that increases a signaling margin of the write data being sampled by the DRAM.

28. The memory controller component of claim 25, wherein the adjusting circuitry comprises circuitry to adjust a phase of a first transmit clock signal that times transmission of the write data.

29. The memory controller component of claim 25, wherein the adjusting circuitry comprises circuitry to adjust the timing of the timing signal such that the timing signal and the first clock signal transition from a low state to a high state at substantially the same time at respective timing signal inputs of the DRAM.

30. The memory controller component of claim 25, wherein the adjusting circuitry comprises clock generation circuitry to generate a plurality of phase-distributed clock signals and an internal clock signal, the plurality of phase-distributed clock signals having phase offsets that are substantially evenly distributed within a cycle time of the internal clock signal, wherein the memory controller adjusts the transmit timing of the write data using clock signals selected from the plurality of phase-distributed clock signals .

31. The memory controller component of claim 25, wherein the timing signal is transmitted such that the propagation of the timing signal from the memory controller component to the DRAM tracks propagation of the write data from the memory controller component to the DRAM.

32. The memory controller component of claim 25, wherein the first clock signal is transmitted such that the propagation of the first clock signal from the memory controller component to the DRAM via a first signal path tracks propagation of the write command from the memory controller component to the DRAM via a second signal path.

33. The memory controller component of claim 25, wherein the second transmitter circuit to transmit the write command to the DRAM comprises circuitry to transmit address information to the DRAM, the address information indicating one or more storage locations within the DRAM at which the write data is to be stored.

34. A memory controller component for controlling a first dynamic random access memory (DRAM) and a second DRAM, the memory controller component comprising:

a first transmitter circuit to transmit a first clock signal to the first DRAM and second DRAM, wherein the first clock signal requires a first time interval to propagate from the memory controller component to the first DRAM and a second time interval to propagate from the memory controller component to the second DRAM, the second time interval being greater than the first time interval;

a second transmitter circuit to transmit a write command to the first DRAM and second DRAM to indicate that first write data is to be stored within the first DRAM and second write data is to be stored within the second DRAM, wherein the write command is sampled by the first DRAM and second DRAM on one or more edges of the first clock signal;

a third transmitter circuit to transmit the first write data to the first DRAM but not the second DRAM, wherein the first write data is sampled by the first DRAM on one or more edges of a first timing signal, wherein the first timing signal requires a third time interval, different from the first time interval, to propagate on a first timing signal wire from the memory controller component to the first DRAM;

a fourth transmitter circuit to transmit the second write data to the second DRAM but not the first DRAM, wherein the second write data is sampled by the second DRAM on one or more edges of a second timing signal, wherein the second timing signal requires a fourth time interval, different from the second time interval, to propagate on a second timing signal wire from the memory controller component to the second DRAM; and

an adjusting circuit to align a rising edge of the first timing signal with a first rising edge of the first clock signal at the first DRAM by adjusting timing of the first timing signal based on the difference between the first time interval and third time interval, and to align a rising edge of the second timing signal with a second rising edge of the first clock signal at the second DRAM by adjusting timing of the second timing signal based on the difference between the second time interval and fourth time interval.

35. The memory controller component of claim 34, wherein the first write data accompanies the first timing signal while the first write data and the first timing signal propagate from the memory controller component to the first DRAM, and the second write data accompanies the second timing signal while the second write data and the second timing signal propagate from the memory controller component to the second DRAM.

36. The memory controller component of claim 34, wherein the first timing signal and second timing signal are a second clock signal and third clock signal, respectively.

37. The memory controller component of claim 34, wherein the adjusting circuit comprises (i) circuitry to adjust the timing of the first timing signal by an amount that increases the signaling margin when the first write data is sampled by the first DRAM, and (ii) circuitry to adjust the timing of the second timing signal by an amount that increases the signaling margin when the second write data is sampled by the second DRAM.

38. The memory controller component of claim 34, wherein the write command and the first clock signal are transmitted to the first and second DRAMs via respective sets of one or more signal lines, wherein each signal line of the respective sets of one or more signal lines is coupled to the first and second DRAMs at different points along its length such that the first clock signal and write command propagate from the memory controller component past the first DRAM to the second DRAM, wherein the first clock signal arrives at the first DRAM before arriving at any other DRAM and the write command arrives at the first DRAM before arriving at any other DRAM.