Symmetrically operating single-ended input buffer devices and methods

• US 8,395,956 B2
• Filed: 10/10/2011
• Issued: 03/12/2013
• Est. Priority Date: 12/18/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yadollah Eslami, Amirabadi
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US13/270,092
• Publication Number:
  US 20120038422A1
• Time in Patent Office: 519 Days
• Field of Search: 365/207, 365/189.05
• US Class Current: 365/207
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H03F 2203/45091 Two complementary type differential amplifiers are paralleled, e.g. one of the p-type and one of the n-type
• CPC Class Codes: H03F 2203/45296 the AAC comprising one or more discrete capacitive elements, e.g. a transistor coupled as capacitor
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance

Abstract

Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One example buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal. The first input node is coupled to the second transistor through a capacitor to mimic the second input node transitioning in the direction opposite to the transition of the input signal.

Claims

1. An input buffer comprising:

an amplifier circuit configured to receive an input signal and a reference signal, the amplifier circuit configured to generate an output signal responsive, at least in part, to the input signal transitioning, the amplifier circuit being capacitively coupled to receive a portion of the input signal in a manner such that a rate at which the amplifier circuit is configured to generate the output signal increases.

2. The input buffer of claim 1, wherein the amplifier circuit is further configured to generate a conditioned signal based, at least in part, on the output signal.

3. The input buffer of claim 2, wherein the amplifier circuit is configured to provide at least one of the output signal or the conditioned signal to column circuitry.

4. The input buffer of claim 1, wherein the amplifier circuit is further configured to generate the output signal based, at least in part, on coupling the input signal to an input transistor.

5. The input buffer of claim 4, further comprising:

a reference transistor capacitively coupled to the input transistor at a first terminal and configured to receive the reference signal at a second terminal, the input transistor further configured to charge and discharge the second terminal responsive, at least in part, to the input signal transitioning.

6. The input buffer of claim 1, wherein the reference signal maintains a constant voltage magnitude.

7. The input buffer of claim 1, wherein the amplifier circuit is coupled between a first supply voltage and a second supply voltage.

8. A method of buffering an output signal comprising:

generating an output signal responsive, at least in part, to an input signal;

capacitively coupling at least a portion of a transition of the input signal in the opposite direction; and

generating the output signal at a rate responsive, at least in part, to the input signal transitioning and said capacitively coupling at least a portion of a transition of the input signal in the opposite direction.

9. The method of claim 8, further comprising:

receiving the input signal at a first input node;

receiving a reference signal at a second input node, wherein the reference signal is maintained at approximately a same voltage.

10. The method of claim 8, wherein said capacitively coupling at least a portion of a transition of the input signal in the opposite direction comprises:

pulling a coupling node toward a supply voltage.

11. The method of claim 8, further comprising:

after said generating the output signal at a rate, conditioning the output signal.

12. The method of claim 11, further comprising:

after said conditioning the output signal, providing a conditioned signal to column circuitry.

13. An method, comprising:

receiving an input signal;

adjusting an ON-resistance of first and second current mirror transistors; and

generating the output signal at a rate based, at least in part, on the input signal,

wherein the rate is based, at least in part, on the adjusted ON-resistance.

14. The method of claim 13, further comprising:

after said receiving an input signal, transitioning a reference signal based, at least in part, on a transition of the input signal.

15. The method of claim 14, wherein the reference signal is transitioned in a direction opposite of the transition of the input signal.

16. The method of claim 13, further comprising:

after said generating the output signal at a rate, providing a conditioned signal based, at least in part, on the output signal.

17. The method of claim 13, wherein said receiving an input signal, comprises:

receiving the input signal at a gate of an input transistor; and

capacitively coupling a node to the gate of the input transistor.

18. The method of claim 13, wherein said adjusting an ON-resistance is based, at least in part, on the input signal.

19. The method of claim 13, wherein the input signal is an analog signal and the output signal is a digital signal.