Wideband mixer

• US 8,396,441 B1
• Filed: 07/09/2008
• Issued: 03/12/2013
• Est. Priority Date: 07/09/2008
• Status: Active Grant

• Current Assignee: Maxlinear Asia Singapore Pte Ltd. (Maxlinear Incorporated)
• Original Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Inventors: Choudhary, Vikas
• Primary Examiner(s): Urban, Edward
• Assistant Examiner(s): HU, RUI MENG
• Application Number:
  US12/170,176
• Time in Patent Office: 1,707 Days
• Field of Search: 455313-333, 455/118, 455/248.1, 455/252.1
• US Class Current: 455/333
• CPC Class Codes: H03D 2200/0088 Reduction of intermodulation, nonlinearities, adjacent channel interference; intercept points of harmonics or intermodulation products
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1458 Double balanced arrangements, i.e. where both input signals are differential

Abstract

A mixer circuit suitable for broadband RF applications is disclosed. A unique biasing scheme for a conventional Gilbert-cell type 4-quadrant multiplier is used, resulting in relatively good linearity, relatively low noise, and relatively low power consumption. Disclosed techniques provide programmability in gain for the mixer and a broadband frequency of operation. A non-linear feedback loop is wrapped around the circuit to stabilize the common-mode voltage shifts due to programming. In one embodiment, a non-linear switch as load-resistance is used to improve the linearity of the circuit.

Claims

1. An apparatus comprising:

a mixing cell comprising a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor, each of which is of a first semiconductor type;

wherein the first MOS transistor is configured to be biased in the linear region of operation, wherein a gate of the first MOS transistor is coupled to a first portion of a first signal;

wherein the second MOS transistor is configured to be biased in the linear region of operation, wherein a gate of the second MOS transistor is coupled to a second portion of the first signal, wherein the second portion is inverted with respect to the first portion;

wherein the third MOS transistor is configured to be biased in the saturation region, wherein a gate of the third MOS transistor is coupled to a first portion of a second signal, wherein a source of the third MOS transistor is coupled to a drain of the first MOS transistor;

wherein the fourth MOS transistor is configured to be biased in the saturation region, wherein a gate of the fourth MOS transistor is coupled to a second portion of the second signal, wherein the second portion is inverted with respect to the first portion, wherein a source of the fourth MOS transistor is coupled to the drain of the first MOS transistor;

wherein the fifth MOS transistor is configured to be biased in the saturation region, wherein a gate of the fifth MOS transistor is coupled to the second portion of the second signal, wherein a source of the fifth MOS transistor is coupled to a drain of the second MOS transistor;

wherein the sixth MOS transistor is configured to be biased in the saturation region, wherein a gate of the sixth MOS transistor is coupled to the first portion of the second signal, wherein a source of the sixth MOS transistor is coupled to the drain of the second MOS transistor;

a seventh MOS transistor of the first semiconductor type with a drain coupled to a source of the first MOS transistor and to a source of the second MOS transistor, wherein the seventh MOS transistor is configured to be a current source or a current sink;

a first load having a first node and a second node, wherein the first node is coupled to a drain of the third MOS transistor and to a drain of the fifth MOS transistor, wherein the second node is coupled to a voltage reference; and

a second load having a first node and a second node, wherein the first node is coupled to a drain of the fourth MOS transistor and to a drain of the sixth MOS transistor, wherein the second node is coupled to the voltage reference;

wherein a first portion of a third signal is available at the first node of the first load and wherein a second portion of the third signal is available at the first node of the second load, wherein the second portion is inverted with respect to the first portion;

wherein each of the first load and the second load comprises a load with a first node and a second node, the load further comprising;

a first resistor having a first node and a second node, the first node of the first resistor coupled to the first node of the load, the second node of the first resistor coupled to the second node of the load;

a second resistor having a first node and a second node, the first node of the second resistor coupled to the first node of the load; and

a MOS transistor of a second semiconductor type different from the first semiconductor type, wherein the MOS transistor is configured as a switch, wherein a drain of the MOS transistor is coupled to the second node of the second resistor, wherein a source of the MOS transistor is coupled to the second node of the load, and wherein a gate of the MOS transistor is coupled to a control for selection of a gain of the mixing cell.

2. The apparatus of claim 1, further comprising a common-mode feedback circuit comprising:

a differential amplifier having a first input, a second input, and an output, wherein the first input is coupled to a source for a common-mode voltage of the third signal, the second input is coupled to a reference voltage for a desired common-mode voltage;

a first feedback-circuit MOS transistor having a gate coupled to the output of the differential amplifier, a drain coupled to the first node of the first load; and

a second feedback-circuit MOS transistor having a gate coupled to the output of the differential amplifier, a drain coupled to the first node of the second load.

3. The apparatus of claim 1, further comprising a common-mode feedback circuit comprising:

a differential amplifier having a first input, a second input, and an output, wherein the first input is coupled to a source for a common-mode voltage of the third signal, the second input is coupled to a reference voltage for a desired common-mode voltage;

a first feedback-circuit MOS transistor having a gate coupled to the output of the differential amplifier, a drain coupled to the first node of the first load; and

a second feedback-circuit MOS transistor having a gate coupled to the output of the differential amplifier, a drain coupled to the first node of the second load.

4. The apparatus of claim 1, wherein each of the first load and the second load are inductorless.

5. The apparatus of claim 1, wherein the first signal is an RF input signal, the second signal is a local oscillator signal, and the third signal is an intermediate frequency or baseband frequency signal.

6. The apparatus of claim 1, wherein the first resistor is in parallel with a series combination of the second resistor and the MOS transistor.

7. The apparatus of claim 1, wherein the first portion of the first signal corresponds to a non-inverted portion of the first signal;

wherein the second portion of the first signal corresponds to an inverted portion of the first signal;

wherein the first portion of the second signal corresponds to a non-inverted portion of the second signal;

wherein the second portion of the second signal corresponds to an inverted portion of the second signal;

wherein the first portion of the third signal corresponds to a non-inverted portion of the third signal;

wherein the second portion of the third signal corresponds to an inverted portion of the third signal.

8. A method of operating a Gilbert cell mixer circuit, the Gilbert cell mixer circuit comprising a first differential pair of MOS transistors, a second differential pair of MOS transistors, and a third differential pair of MOS transistor, the method comprising:

biasing the first differential pair into the linear or ohmic region and not to the saturation region, wherein a gate of a first MOS transistor of the first differential pair is coupled to a first portion of a first signal, and wherein a gate of a second MOS transistor of the first differential pair is coupled to a second portion of a first signal;

biasing the second differential pair into the saturation region, wherein sources of the second differential pair are coupled to a drain of the first MOS transistor of the first differential pair;

biasing the third differential pair into the saturation region, wherein sources of the third differential pair are coupled to a drain of the second MOS transistor of the first differential pair;

wherein a gate of a first MOS transistor of the second differential pair and a gate of a second MOS transistor of the third differential pair are coupled to a first portion of a second signal;

wherein a gate of a second MOS transistor of the second differential pair and a gate of a first MOS transistor of the third differential pair are coupled to a second portion of the second signal;

wherein a first portion of a third signal is available at a first node coupling a drain of the first MOS transistor of the second differential pair and a drain of the first MOS transistor of the third differential pair and wherein a second portion of the third signal is available at a drain of the second MOS transistor of the second differential pair and a drain of the second MOS transistor of the third differential pair; and

controllably switching an amount of load resistance applied to sources of the second differential pair and the third differential pair to change a gain associated with the Gilbert cell mixer circuit.

9. The method of claim 8, wherein the first signal is an RF input signal, the second signal is a local oscillator signal, and the third signal is an intermediate frequency or baseband frequency signal.

10. The method of claim 8, further comprising controlling a common-mode voltage of the third signal, the method further comprising:

comparing the common-mode voltage of the third signal to a reference voltage; and

using feedback control based on the comparison to generate a control voltage for gates of a first feedback-circuit transistor and a second feedback-circuit transistor for control of the common mode voltage of the third signal.

11. The method of claim 8, further comprising controlling a common-mode voltage of the third signal, the method further comprising:

comparing the common-mode voltage of the third signal to a reference voltage; and

using feedback control based on the comparison to generate a control voltage for gates of a first feedback-circuit transistor and a second feedback-circuit transistor for control of the common mode voltage of the third signal.

12. The method of claim 8, wherein a first resistor is in parallel with a series combination of a second resistor and a MOS transistor, wherein switching further comprises switching the MOS transistor.

13. The method of claim 8, wherein the first portion of the first signal corresponds to a non-inverted portion of the first signal;

wherein the second portion of the first signal corresponds to an inverted portion of the first signal;

wherein the first portion of the second signal corresponds to a non-inverted portion of the second signal;

wherein the second portion of the second signal corresponds to an inverted portion of the second signal;

wherein the first portion of the third signal corresponds to a non-inverted portion of the third signal;

wherein the second portion of the third signal corresponds to an inverted portion of the third signal.