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Matrix decomposition in an integrated circuit device

  • US 8,396,914 B1
  • Filed: 09/11/2009
  • Issued: 03/12/2013
  • Est. Priority Date: 09/11/2009
  • Status: Active Grant
First Claim
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1. Matrix decomposition circuitry for triangulating an input matrix to create a resultant matrix having a plurality of resultant matrix elements on a diagonal, and having a further plurality of resultant matrix elements arranged in columns below said resultant matrix elements on said diagonal, and having no nonzero matrix elements in said columns above said resultant matrix elements on said diagonal, said matrix decomposition circuitry comprising:

  • an inner product computation path including a plurality of multipliers and adders for computing respective inner products of row vectors of said resultant matrix corresponding to respective elements of said input matrix, and a subtractor for subtracting each said respective inner product from said respective element of said input matrix to output respective inner product difference elements corresponding to said respective elements of said input matrix;

    an inverse square root multiplication path including a first storage element for latching a particular one of said respective inner product difference elements, inverse square root circuitry that computes an inverse square root of said particular one of said respective inner product difference elements, and a multiplier that multiplies said inverse square root by an output of said inner product computation path; and

    a pipeline stage between said inner product computation path and said inverse square root multiplication path;

    whereby;

    each of said respective inner product difference elements is multiplied by said inverse square root of said particular one of said respective inner product difference elements to output a respective one of resultant matrix elements.

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