Hybrid memory module

• US 8,397,013 B1
• Filed: 03/27/2008
• Issued: 03/12/2013
• Est. Priority Date: 10/05/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rosenband, Daniel L., Weber, Frederick Daniel, Smith, Michael John Sebastian
• Primary Examiner(s): Chery, Mardochee
• Application Number:
  US12/057,306
• Time in Patent Office: 1,811 Days
• Field of Search: 711/102, 711/103, 711/104, 711/105, 711/111, 711/148, 711/154, 365/205
• US Class Current: 711/103
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19107 off-chip wires

Abstract

One embodiment of the present invention sets forth a hybrid memory module that combines memory devices of different types while presenting a single technology interface. The hybrid memory module includes a number of super-stacks and a first interface configured to transmit data between the super-stacks and a memory controller. Each super-stack includes a number of sub-stacks, a super-controller configured to control the sub-stacks, and a second interface configured to transmit data between the sub-stacks and the first interface. Combining memory devices of different types allows utilizing the favorable properties of each type of the memory devices, while hiding their unfavorable properties from the memory controller.

Claims

1. A hybrid memory module, comprising:

a plurality of super-stacks; and

a host interface configured to transmit data between the plurality of super-stacks and a memory controller,

wherein each super-stack includes;

a respective plurality of sub-stacks, each of the sub-stacks including;

a respective sub-controller, a plurality of memory devices of a first memory type and a memory device of a second memory type,

a respective super-controller configured to control the plurality of sub-stacks, and

a respective super-stack interface configured to transmit data between the plurality of sub-stacks and the host interface.

2. The hybrid memory module of claim 1, wherein each respective sub-controller is configured to control the plurality of memory devices of the first memory type, and wherein each sub-stack further includes:

a respective interface configured to transmit data between the sub-controller and the super-controller.

3. The hybrid memory module of claim 2, wherein each sub-controller includes:

the respective memory device of the second memory type;

a respective plurality of flash controllers configured to provide interface, mapping, error detection, or error correction functionality to the plurality of memory devices of the first memory type; and

a respective flash interface configured to transmit data between the plurality of flash controllers and the plurality of memory devices of the first memory type.

4. The hybrid memory module of claim 3, wherein:

the number of flash controllers within the plurality of flash controllers is equal to the number of memory devices within the plurality of memory devices of the first memory type, and

each flash controller provides interface, mapping, error detection, and error correction functionality to only one of the plurality of the memory devices of the first memory type.

5. The hybrid memory module of claim 3, wherein the plurality of flash controllers are implemented in a single block.

6. The hybrid memory module of claim 3, wherein the sub-controller further includes command queuing logic configured to:

receive first data from the plurality of memory devices of the first memory type and the memory device of the second memory type;

multiplex the first data to produce multiplexed data; and

transmit the multiplexed data to the super-controller via the interface.

7. The hybrid memory module of claim 6, wherein the command queuing logic is further configured to:

receive second data from the super-controller via the interface;

demultiplex the received second data to produce demultiplexed data; and

transmit the demultiplexed data to at least one of the plurality of memory devices of the first memory type via the flash interface and the memory device of the second memory type.

8. The hybrid memory module of claim 3, wherein the sub-controller further includes high-speed interface logic configured to convert the data communicated via the interface to the data communicated via the flash interface.

9. The hybrid memory module of claim 3, wherein the super-controller includes a signaling translation unit configured to translate data, clock, command, and control signals from a first memory channel protocol having a first signaling speed to a second memory channel protocol having a second signaling speed, the second signaling speed being different from the first signaling speed.

10. The hybrid memory module of claim 3, wherein the super-controller includes protocol logic configured to convert a first protocol used to transmit data via the interface to a second protocol.

11. The hybrid memory module of claim 3, wherein the super-controller includes logic configured to match the speed of each memory device of the first memory type with the speed of the memory device of the second memory type.

12. The hybrid memory module of claim 3, wherein the first memory type comprises non-volatile memory.

13. The hybrid memory module of claim 12, wherein the non-volatile memory comprises NAND flash memory.

14. The hybrid memory module of claim 12, wherein the sub-stack includes a spare device.

15. The hybrid memory module of claim 3, wherein the second memory type comprises volatile memory.

16. The hybrid memory module of claim 15, wherein the volatile memory comprises Static Random Access Memory (SRAM) memory.

17. The hybrid memory module of claim 1, wherein the hybrid memory module comprises a dual inline memory module (DIMM).

18. The hybrid memory module of claim 1, wherein the hybrid memory module is part of a memory subsystem.

19. The hybrid memory module of claim 1, wherein the hybrid memory module is coupled to a motherboard.

20. The hybrid memory module of claim 1, wherein the hybrid memory module is included in a computer system.

21. A hybrid memory module, comprising:

a plurality of super-stacks; and

a host interface configured to transmit data between the plurality of super-stacks and a memory controller,

wherein each super-stack includes;

a plurality of sub-stacks, each of the sub-stacks including;

a respective plurality of non-volatile memory devices;

a respective sub-controller configured to control the plurality of non-volatile memory devices, the sub-controller including a volatile memory device; and

a respective interface configured to transmit data between the sub-controller and a super-controller; and

the super-controller configured to control the plurality of sub-stacks, and

a super-stack interface configured to transmit data between the plurality of sub-stacks and the first interface.

22. The hybrid memory module of claim 21, wherein each sub-controller includes:

a respective plurality of flash controllers configured to provide interface, mapping, error detection, or error correction functionality to the plurality of non-volatile memory devices; and

a respective flash interface configured to transmit data between the plurality of flash controllers and the plurality of non-volatile memory devices.

23. The hybrid memory module of claim 22, wherein:

the number of flash controllers within the plurality of flash controllers is equal to the number of non-volatile memory devices within the plurality of non-volatile memory devices, and

each flash controller provides interface, mapping, error detection, and error correction functionality to only one of the plurality of non-volatile memory devices.

24. The hybrid memory module of claim 22, wherein the plurality of flash controllers are implemented in a single block.

25. The hybrid memory module of claim 22, wherein the sub-controller further includes command queuing logic configured to:

receive first data from at least two of the plurality of non-volatile memory devices;

multiplex the first data to produce multiplexed data; and

transmit the multiplexed data to the super-controller via the interface.

26. The hybrid memory module of claim 25, wherein the command queuing logic is further configured to:

receive second data from the super-controller via the interface;

demultiplex the received second data to produce demultiplexed data; and

transmit the demultiplexed data to at least two of the plurality of non-volatile memory devices via the flash interface.

27. The hybrid memory module of claim 22, wherein the sub-controller further includes high-speed interface logic configured to convert the data communicated via the interface to the data communicated via the flash interface.

28. The hybrid memory module of claim 22, wherein the super-controller includes a signaling translation unit configured to translate data, clock, command, and control signals from a first memory channel protocol having a first signaling speed to a second memory channel protocol having a second signaling speed, the second signaling speed being different from the first signaling speed.

29. The hybrid memory module of claim 22, wherein the super-controller includes protocol logic configured to convert a first protocol used to transmit data via the interface to a second protocol.

30. A hybrid memory module, comprising:

a plurality of super-stacks; and

a host interface configured to transmit data between the plurality of super-stacks and a memory controller,

wherein each super-stack includes;

a plurality of sub-stacks, each of the sub-stacks including;

a respective plurality of flash memory devices;

a respective sub-controller configured to control the plurality of flash memory devices, the sub-controller including;

a volatile memory device;

a respective plurality of flash controllers configured to provide interface, mapping, error detection, or error correction functionality to the plurality of flash memory devices, the respective plurality of flash controllers being equal in number to the flash memory devices; and

a respective flash interface configured to transmit data between the plurality of flash controllers and the plurality of flash memory devices;

a respective interface configured to transmit data between the sub-controller and a super-controller; and

the super-controller configured to control the plurality of sub-stacks, and

a super-stack interface configured to transmit data between the plurality of sub-stacks and the host interface.

31. The hybrid memory module of claim 30, wherein the plurality of flash controllers are implemented in a single block.

32. The hybrid memory module of claim 30, wherein the sub-controller further includes command queuing logic configured to:

receive first data from at least two of the plurality of non-volatile memory devices;

multiplex the first data to produce multiplexed data; and

transmit the multiplexed data to the super-controller via the interface.

33. The hybrid memory module of claim 32, wherein the command queuing logic is further configured to:

receive second data from the super-controller via the interface;

demultiplex the received second data to produce demultiplexed data; and

transmit the demultiplexed data to at least two of the plurality of non-volatile memory devices via the flash interface.

34. The hybrid memory module of claim 30, wherein the sub-controller further includes high-speed interface logic configured to convert the data communicated via the interface to the data communicated via the flash interface.

35. The hybrid memory module of claim 30, wherein the super-controller includes a signaling translation unit configured to translate data, clock, command, and control signals from a first memory channel protocol having a first signaling speed to a second memory channel protocol having a second signaling speed, the second signaling speed being different from the first signaling speed.

36. The hybrid memory module of claim 30, wherein the super-controller includes protocol logic configured to convert a first protocol used to transmit data via the interface to a second protocol.