Memory control device and semiconductor processing apparatus
First Claim
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1. A semiconductor device comprising:
- a system bus;
a CPU coupled to the system bus; and
a memory controller coupled to the system bus and which receives command information from the CPU and time interval information that specifies a time interval as a wait time until the next command information is issued to an external semiconductor memory,wherein the memory controller comprisesa register for storing the command information and the time interval information; and
a determining unit for determining whether issue of the command information stored in the register has been completed or not,wherein when an inquiry of whether issue of the command information is completed or not is received from the CPU, the determining unit replies whether issue of the command information has been completed or not.
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Abstract
The present invention provides a memory control device and a semiconductor processing apparatus which can be flexibly made adapted to a plurality of kinds of semiconductor memories. An SDRAM controller has: a register unit to which a command to be issued and a minimum interval (wait time) between issue of the command and issue of the next command are written by a CPU; and a command issuing unit that stops issue of the next command until the minimum interval written in the register elapses since issue of the command written in the register. Therefore, by changing software for the CPU, the SDRAM controller can be flexibly adapted to a plurality of kinds of SDRAMs.
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Citations
2 Claims
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1. A semiconductor device comprising:
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a system bus; a CPU coupled to the system bus; and a memory controller coupled to the system bus and which receives command information from the CPU and time interval information that specifies a time interval as a wait time until the next command information is issued to an external semiconductor memory, wherein the memory controller comprises a register for storing the command information and the time interval information; and a determining unit for determining whether issue of the command information stored in the register has been completed or not, wherein when an inquiry of whether issue of the command information is completed or not is received from the CPU, the determining unit replies whether issue of the command information has been completed or not. - View Dependent Claims (2)
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Specification
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Current AssigneeRenesas Electronics Corporation
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Original AssigneeRenesas Electronics Corporation
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InventorsImai, Rintaro, Nakano, Satoshi
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Primary Examiner(s)YU, JAE UN
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Application NumberUS13/406,262Publication NumberTime in Patent Office379 DaysField of Search711/150, 711/154, 711/167, 711/168, 708/273US Class Current711/154CPC Class CodesG06F 13/1689 Synchronisation and timing ...
