Multi-phased computational reconfiguration
First Claim
Patent Images
1. A method for dynamically reconfiguring a processing device, comprising:
- providing a reconfigurable processing device, the processing device being at least partially reconfigurable from a first computational structure configured to process data with a first precision at a first computational speed to a second computational structure configured to process data with a second precision at a second computational speed, the second precision and second computational speed being different than the first precision and the first computational speed;
processing data with the first computational structure in a first computational phase to produce a first phase solution;
then dynamically reconfiguring at least a portion of the processing device from the first computational structure to the second computational structure; and
then processing data of the first phase solution with the second computational structure in a second computational phase to produce a second phase solution.
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Abstract
Problem solution speed may be increased by dynamically changing processing device computational hardware configuration in concert with respective mathematical phases of an algorithm to match accuracy demands at various phases of computation. Smaller but faster hardware structures may be increased in size using real-time partial or full reconfiguration of a processing device to apply the smallest and fastest possible computational structure for the needed accuracy during each of multiple computational phases.
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Citations
21 Claims
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1. A method for dynamically reconfiguring a processing device, comprising:
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providing a reconfigurable processing device, the processing device being at least partially reconfigurable from a first computational structure configured to process data with a first precision at a first computational speed to a second computational structure configured to process data with a second precision at a second computational speed, the second precision and second computational speed being different than the first precision and the first computational speed; processing data with the first computational structure in a first computational phase to produce a first phase solution; then dynamically reconfiguring at least a portion of the processing device from the first computational structure to the second computational structure; and then processing data of the first phase solution with the second computational structure in a second computational phase to produce a second phase solution. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system for dynamically reconfiguring a processing device, comprising:
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a reconfigurable processing device configured with a first computational structure configured to process data with a first precision at a first computational speed, the processing device being at least partially reconfigurable from the first computational structure to a second computational structure configured to process data with a second precision at a second computational speed, the second precision and second computational speed being different than the first precision and the first computational speed; and a computer processing system coupled by a datapath to the reconfigurable processing device, the computer processing system including memory and the second computational structure being prefigured in the memory of the computer processing system; where the computer processing system is configured to dynamically reconfigure at least a portion of the processing device from the first computational structure to the second computational structure after data is processed with the first computational structure in a first computational phase to produce a first phase solution and before data of the first phase solution is processed with the second computational structure in a second computational phase to produce a second phase solution. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A method for dynamically reconfiguring a processing device, comprising:
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providing a reconfigurable processing device configured to execute a mathematical algorithm having multiple phases; and dynamically changing the configuration of the reconfigurable processing device while executing the algorithm on the reconfigurable processing device from a first computational structure corresponding to the accuracy requirements of a first phase of the mathematical algorithm to a second computational structure corresponding to the accuracy requirements of a second phase of the mathematical algorithm; where the mathematical algorithm is an iterative algorithm, where the accuracy requirements of the second phase of the mathematical algorithm is greater than the accuracy requirements of the first phase of the mathematical algorithm and where the method further comprises; executing the first phase of the mathematical algorithm on the reconfigurable processing device using the first computational structure with a first precision at a first computational speed prior to dynamically changing the configuration of the reconfigurable processing device , and initiating the second mathematical algorithm phase starting with data produced during the first mathematical algorithm phase, and executing the second phase of the mathematical algorithm on the reconfigurable processing device using the second computational structure with a second precision at a second computational speed after dynamically changing the configuration of the reconfigurable processing device, the second precision being higher than the first precision and the first computational speed being faster than the second computational speed. - View Dependent Claims (19, 20, 21)
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Specification