Field configured electronic circuits and methods of making the same

• US 8,397,198 B1
• Filed: 12/12/2011
• Issued: 03/12/2013
• Est. Priority Date: 03/17/2008
• Status: Active Grant

• Current Assignee: Ensurge Micropower ASA
• Original Assignee: Kovio Incorporated (Ensurge Micropower ASA)
• Inventors: Li, Jiang
• Primary Examiner(s): LIN, SUN J
• Application Number:
  US13/323,279
• Time in Patent Office: 456 Days
• Field of Search: 716/100, 716/118, 716/119, 716/139, 716/110, 716/121, 716/128
• US Class Current: 716/118
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

Semiconductor devices and/or structures, and methods for fabricating the same are disclosed. Embodiments of the present invention allow for production of customized products, while also minimizing production steps, avoiding some or all photolithography steps, and reducing overall production costs. Using selective deposition and patterning methods such as printing, to form metal and/or dielectric layer(s) on substrates where one or more device circuit components are pre-made in a factory, but which require further processing to obtain an electrically functional circuit, results in the ability for a user/consumer to make custom, specific and/or unique electrically functional circuits without incurring the cost and complexity of a full fabrication to form and pattern all of the layers.

Claims

1. A method of field programming an integrated circuit, comprising:

a) inputting logic and/or circuit functions into a computer configured to design one or more circuit layouts;

b) designing the one or more circuit layouts from the logic and/or circuit functions; and

c) printing one or more metal layers on or over a transistor array on a substrate, according to the one or more circuit layouts.

2. The method of claim 1, further comprising correcting the one or more circuit layouts and providing the one or more circuit layouts directly to a printing device, wherein said one or more metal layers are printed according to the corrected one or more circuit layouts.

3. The method of claim 2, wherein correcting the one or more circuit layouts comprises one or more processes including converting, resampling, and/or reprocessing the circuit layout to produce a working bitmap;

determining and applying a set of correction rules; and

/or manually manipulating the circuit layout.

4. The method of claim 1, wherein printing the one or more metal layers comprises inkjet printing, micro-spotting, pen-coating, syringe dispensing, pump dispensing, vapor-jet printing, gravure printing, offset lithography, flexographic printing, stamping, or screen printing an ink comprising a metal precursor in a solvent.

5. The method of claim 1, further comprising forming a dielectric layer on the transistor array prior to printing the one or more metal layers.

6. A method of field-configuring a circuit, comprising:

a) depositing a first metal ink according to a predetermined wiring pattern on or over a substrate having (i) an array of transistors thereon and (ii) a first dielectric layer on the transistors, the first dielectric layer having a first plurality of contact openings therein, wherein the predetermined wiring pattern enables functionality and/or logic in a circuit comprising the transistors and the predetermined wiring pattern; and

b) forming a first plurality of patterned metal lines from the first metal ink.

7. The method of claim 6, comprising depositing the first metal ink in some or all of the first plurality of contact openings.

8. The method of claim 6, wherein the array of transistors comprises a plurality of rows and a plurality of columns, wherein each intersection of one row and one column defines a location of one transistor in the array.

9. The method of claim 6, wherein the substrate comprises a single crystal silicon wafer, a metal sheet, a metal foil, a plastic sheet, a plastic film, a plastic web, a glass sheet or a glass slip.

10. The method of claim 6, further comprising printing the first dielectric layer on the substrate, wherein the first plurality of contact openings is formed in the first dielectric layer after printing the first dielectric layer, to expose the terminals of the transistors.

11. The method of claim 10, comprising selectively printing the first dielectric layer in a pattern covering portions of the transistors and exposing the terminals of the transistors.

12. The method of claim 10, wherein the first dielectric layer comprises an N- and/or P-dopant.

13. The method of claim 6, wherein depositing the first metal ink comprises inkjet printing, gravure printing, off-set lithography, screen printing, flexographic printing, microspotting, pen-coating, laser writing, syringe dispensing, stencil printing, and/or pump dispensing the metal ink.

14. The method of claim 6, wherein the first dielectric layer has a first layer of patterned metal wires thereon electrically connected to the transistors in the array, and the substrate further comprises a second dielectric layer on the first layer of patterned metal wires having a second plurality of contact openings therein.

15. The method of claim 6, wherein the transistors comprise thin film transistors.

16. The method of claim 6, wherein the first metal ink comprises a metal precursor material and a solvent, wherein the metal precursor material is present in an amount of 1 to 50 wt. % of the ink, and the metal precursor material is soluble in the solvent.

17. The method of claim 16, wherein the metal precursor material comprises metal nanoparticles and/or a metal compound of aluminum, titanium, vanadium, copper, silver, chromium, molybdenum, tungsten, cobalt, nickel, gold, palladium, platinum, zinc, and/or iron.

18. The method of claim 16, comprising drying the first metal ink to remove the solvent and form a dried metal-containing material, and annealing the dried metal-containing material to form the first plurality of patterned metal lines.

19. The method of claim 6, further comprising:

a) forming a second dielectric layer on the first plurality of patterned metal lines, the second dielectric layer having a second plurality of contact openings therein exposing portions of the first plurality of patterned metal lines, b) printing a second metal ink on the second dielectric layer, and c) forming a second plurality of patterned metal lines from the printed second metal ink.

20. The method of claim 6, wherein forming the first plurality of patterned metal lines comprises printing a seed layer and then forming a bulk conductive layer on the seed layer.