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Three dimensional integration with through silicon vias having multiple diameters

  • US 8,399,180 B2
  • Filed: 01/14/2010
  • Issued: 03/19/2013
  • Est. Priority Date: 01/14/2010
  • Status: Active Grant
First Claim
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1. A method comprising:

  • patterning a photoresist layer on a substrate of a structure having at least one conductor embedded therein;

    removing a first portion of the photoresist layer to expose a first area of the substrate;

    etching the first area to form a cavity having a first depth;

    removing a second portion of the photoresist to expose an additional area of the substrate; and

    etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure.

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