Capacitive micromachined ultrasonic transducer and manufacturing method

• US 8,399,278 B2
• Filed: 12/21/2010
• Issued: 03/19/2013
• Est. Priority Date: 09/15/2004
• Status: Active Grant

• Current Assignee: Sonetics Ultrasound, Inc.
• Original Assignee: Sonetics Ultrasound, Inc.
• Inventors: Lemmerhirt, David F., Rich, Collin A.
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US12/974,349
• Publication Number:
  US 20110151608A1
• Time in Patent Office: 819 Days
• Field of Search: 257/254
• US Class Current: 438/51
• CPC Class Codes: A61B 8/00 Diagnosis using ultrasonic, sonic or infrasonic waves imaging of objects using sonar G01S15/00
• CPC Class Codes: A61B 8/4472 Wireless probes
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type

Abstract

The integrated circuit/transducer device of the preferred embodiment includes a substrate, a complementary-metal-oxide-semiconductor (CMOS) circuit that is fabricated on the substrate, and a capacitive micromachined ultrasonic transducer (cMUT) element that is also fabricated on the substrate. The CMOS circuit and cMUT element are fabricated during the same foundry process and are connected. The cMUT includes a lower electrode, an upper electrode, a membrane structure that support the upper electrode, and a cavity between the upper electrode and lower electrode.

Claims

1. A method of producing an integrated circuit/transducer device, the method comprising the steps of:

providing a substrate;

fabricating a complementary-metal-oxide-semiconductor (CMOS) circuit on the substrate;

fabricating a capacitive micromachined ultrasonic transducer (cMUT) element on the substrate and connecting the cMUT element to the CMOS circuit, wherein the cMUT element includes the following components that consist of layers corresponding to layers within the CMOS circuit;

a lower electrode, an upper electrode, and a sacrificial layer located between the lower electrode and the upper electrode;

leaving a passivation opening that substantially encircles the upper electrode;

removing the sacrificial layer, thereby defining a cavity between the lower electrode and the upper electrode and creating a membrane structure above the cavity; and

depositing a sealant layer thereby sealing the cavity.

2. The method of claim 1 wherein the outer region of the membrane structure is substantially thinner than the central region of the membrane structure.

3. The method of claim 2 wherein the passivation opening is above a ring of sacrificial material that substantially encircles the upper electrode.

4. The method of claim 3 further including removing the ring of a sacrificial material.

5. The method of claim 2 further including creating at least one electrical conductor spanning the membrane structure and that connects to the upper electrode.

6. The method of claim 5 wherein the at least one electrical conductor is arranged to achieve symmetric mechanical rigidity.

7. The method of claim 6 wherein three electrical conductors are arranged radially and equally spaced around the upper electrode that is circularly shaped.

8. The method of claim 5 further including etching at least one etch port along the membrane perimeter and near an electrical connector.

9. The method of claim 8 wherein the ring of sacrificial material is first removed and then the sacrificial layer is removed via the etch port.