Methods of forming and assembling pre-encapsulated assemblies and of forming associated semiconductor device packages

• US 8,399,297 B2
• Filed: 10/20/2011
• Issued: 03/19/2013
• Est. Priority Date: 04/24/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yean, Tay Wuu, Ai-Chie, Wang
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US13/277,988
• Publication Number:
  US 20120034740A1
• Time in Patent Office: 516 Days
• Field of Search: 257/E25.017, 257/E21.614, 257/E21.502, 257/685, 257/686, 257/690, 257/698, 257/723, 257/777, 438/64, 438107-109, 438/117, 438/125, 427/58, 361/760
• US Class Current: 438/107
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1017 the lowermost container comprising a device support
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1052 Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49861 Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 27/14618 : Containers
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80

Abstract

Methods of forming pre-encapsulated frames comprise flowing a dielectric encapsulation material around at least one conductive trace. A cavity configured to receive at least one semiconductor device at least partially in the cavity is formed in the encapsulation material. A first connection area of the at least one trace is exposed within the cavity. At least another connection area of the at least one trace is exposed laterally adjacent to the cavity. The dielectric encapsulation material is hardened to form a pre-encapsulated frame.

Claims

1. A method of assembling a pre-encapsulated assembly comprising:

attaching an imaging semiconductor device to a first encapsulated structure having a cavity therein, the cavity having a portion of the first encapsulated structure extending thereover, another portion extending therearound, an aperture in the top thereof and a plurality of traces located in the first encapsulated structure, each trace having a first portion extending in the portion of the first encapsulated structure extending over the cavity and a second portion extending in the another portion of the encapsulated member connected to the first portion, one end of the second portion being exposed for connection thereto;

dispensing an adhesive contacting a portion of the first encapsulated structure and a portion of the imaging semiconductor device;

attaching a transparent member to the first encapsulated structure by contacting the adhesive;

sealing the cavity in the encapsulated member using a liquid encapsulant material; and

placing solder material on the first encapsulated structure in a pattern on the second portions of at least some traces.

2. The method of claim 1, further comprising connecting the second portion of at least one trace of the plurality of traces to a connection area of second encapsulated structure to electrically connect the imaging semiconductor device to at least one of a DRAM and a NAND Flash memory semiconductor device.

3. A method of forming a pre-encapsulated frame, comprising:

flowing a dielectric encapsulating compound around at least one conductive trace;

controlling flow of the dielectric encapsulating compound to form a cavity configured to receive at least one semiconductor device at least partially in the cavity in the encapsulation material;

controlling flow of the dielectric encapsulating compound to leave exposed a first connection area of the at least one trace at a first depth within the cavity for connection to a first semiconductor device;

controlling flow of the dielectric encapsulating compound to leave exposed a second connection area of the at least one trace at a second, different depth within the cavity for connection to a second semiconductor device;

controlling flow of the dielectric encapsulating compound to leave exposed at least another connection area of the at least one trace laterally adjacent to the cavity; and

hardening the dielectric encapsulating compound to form a pre-encapsulated frame.

4. The method of claim 3, wherein controlling flow of the dielectric encapsulating compound to leave exposed the first connection area of the at least one trace within the cavity comprises controlling flow of the dielectric encapsulating compound to leave exposed a plurality of first connection areas of a plurality of traces within the cavity.

5. The method of claim 4, wherein controlling flow of the dielectric encapsulating compound to leave exposed the plurality of first connection areas of the plurality of traces within the cavity comprises:

controlling flow of the dielectric encapsulating compound to leave exposed at least one first connection area of the plurality of first connection areas associated with a first trace of the plurality of traces at the first depth within the cavity for connection to a first semiconductor device; and

controlling flow of the dielectric encapsulating compound to leave exposed at least another first connection area of the plurality of first connection areas associated with another trace of the plurality of traces at a third, different depth within the cavity for connection to the second semiconductor device.

6. The method of claim 3, further comprising forming a central aperture configured to transmit light to an imaging semiconductor device above the cavity.

7. A method of forming a semiconductor device package, comprising:

flowing a dielectric encapsulation material around a plurality of conductive traces;

controlling flow of the dielectric encapsulation material to form a cavity configured to receive at least one semiconductor device at least partially in the cavity in the encapsulation material;

controlling flow of the dielectric encapsulation material to leave exposed a plurality of first connection areas of the plurality of traces within the cavity, wherein at least one first connection area of the plurality of first connection areas of a first trace of the plurality of traces is exposed at a first depth within the cavity for connection to a first semiconductor device and at least another first connection area of the plurality of first connection areas of another trace of the plurality of traces is exposed at a second, different depth within the cavity for connection to a second semiconductor device;

controlling flow of the dielectric encapsulation material to leave exposed at least another connection area of the first trace laterally adjacent to the cavity;

hardening the dielectric encapsulation material to a pre-encapsulated frame;

disposing at least one semiconductor device at least partially in the cavity with an active surface of the at least one semiconductor device facing the at least one first connection area of the first trace; and

connecting the at least one first connection area of the first trace to the active surface of the at least one semiconductor device.

8. The method of claim 7, further comprising connecting the at least another first connection area to a second semiconductor device.

9. The method of claim 7, further comprising:

exposing a third connection area of the first trace at a third, different depth within the cavity for connection to a second semiconductor device.

10. The method of claim 9, further comprising connecting the third connection area to a second semiconductor device.

11. The method of claim 7, further comprising forming a central aperture above the cavity to transmit light to the semiconductor device, wherein the semiconductor device comprises an imaging semiconductor device.

12. The method of claim 7, further comprising connecting a plurality of first connection areas of a plurality of first traces to the active surface of the at least one semiconductor device along one side of the at least one semiconductor device.

13. The method of claim 12, wherein connecting the plurality of first connection areas of the plurality of first traces to the active surface of the at least one semiconductor device along the one side of the at least one semiconductor device comprises connecting the plurality of first connection areas to the active surface of the at least one semiconductor device along a long side of the at least one semiconductor device.

14. The method of claim 7, further comprising connecting a plurality of first connection areas of a plurality of first traces to bond pads on the active surface of the at least one semiconductor device in a 1.5-sided configuration.

15. The method of claim 7, further comprising connecting a plurality of first connection areas of a plurality of first traces to bond pads on the active surface of the at least one semiconductor device in a 2-sided configuration.

16. The method of claim 7, further comprising flowing an encapsulant material into the cavity with the semiconductor device.

17. The method of claim 7, further comprising connecting the at least another connection area of the at least one trace to a connection area of at least a second pre-encapsulated frame stacked with the pre-encapsulated frame.