Through-silicon via with low-K dielectric liner

• US 8,399,354 B2
• Filed: 11/12/2009
• Issued: 03/19/2013
• Est. Priority Date: 01/13/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ming-Fa
• Primary Examiner(s): Lee, Calvin
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US12/617,259
• Publication Number:
  US 20100176494A1
• Time in Patent Office: 1,223 Days
• Field of Search: 257/774, 257/E23.011, 257/E21.597, 438/667
• US Class Current: 438/667
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/059 : Being combinations of any of the materials from the groups H01L2924/042 - H01L2924/0584, e.g. oxynitrides
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the first liner, which is subsequently removed and a second liner formed with a low-k or extra low-k dielectric is formed in its place.

Claims

1. A method of forming a semiconductor device, the method comprising:

providing a substrate, the substrate having a first side and a second side opposite the first side;

forming an opening extending from the first side of the substrate into the substrate;

forming a first liner along sidewalls of the opening;

forming a conductive material over the first liner in the opening;

thinning the second side of the substrate, thereby exposing at least a portion of the first liner;

removing at least a portion of the first liner interposed between the conductive material and the substrate and removing at least a portion of the first liner extending over a dielectric layer on the first side of the substrate; and

forming, after the removing, a second liner interposed between the conductive material and the substrate and extending over at least a portion of the dielectric layer formed on the first side of the substrate.

2. The method of claim 1, wherein the second liner comprises a material having a dielectric constant less than about 3.5.

3. The method of claim 1, wherein the first liner comprises a material having a dielectric constant greater than about 3.5.

4. The method of claim 1, wherein the second liner comprises polyimide.

5. The method of claim 1, wherein the thinning the second side of the substrate includes etching the second side of the substrate such that a portion of the conductive material protrudes from the second side of the substrate.