Substrates having voltage switchable dielectric materials

• US 8,399,773 B2
• Filed: 01/27/2010
• Issued: 03/19/2013
• Est. Priority Date: 01/27/2009
• Status: Expired due to Fees

• Current Assignee: Littelfuse Incorporated
• Original Assignee: Shocking Technologies, Inc.
• Inventors: Kosowsky, Lex, Graydon, Bhret, Moustafaev, Djabbar, Shang, Shurui, Fleming, Robert
• Primary Examiner(s): Datskovskiy, Michail V
• Application Number:
  US12/694,702
• Publication Number:
  US 20100187006A1
• Time in Patent Office: 1,147 Days
• Field of Search: 174250-267, 174/350, 361760-767, 361777-782, 361/792, 361794-795, 361/824, 29825-852, 257/687, 257/782, 257/668, 257/678, 257700-703, 257/734, 257/758, 257/737, 257/738, 257/698, 257690-693, 257/530, 257/779, 438/700, 438/99, 438106-118, 438/623, 428/212, 428/322, 428/137, 428/209, 428/446, 428/114, 428/412, 428/416, 428/3, 428/299.1, 428/489, 428/697, 428/297.4, 428/210
• US Class Current: 174/250
• CPC Class Codes: H05K 1/0259 Electrostatic discharge [ESD] protection
• CPC Class Codes: H05K 1/0271 Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
• CPC Class Codes: H05K 1/036 Multilayers with layers of different types
• CPC Class Codes: H05K 1/0373 containing additives, e.g. fillers H05K1/036 takes precedence
• CPC Class Codes: H05K 2201/068 wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 2201/0738 Use of voltage responsive materials, e.g. voltage switchable dielectric or varistor materials
• CPC Class Codes: H05K 2201/09136 Means for correcting warpage
• CPC Class Codes: H05K 3/0005 for designing circuits by computer
• CPC Class Codes: Y10T 428/24917 including metal layer
• CPC Class Codes: Y10T 428/24942 including components having same physical characteristic in differing degree

Abstract

Various aspects provide for incorporating a VSDM into a substrate to create an ESD-protected substrate. In some cases, a VSDM is incorporated in a manner that results in the ESD-protected substrate meeting one or more specifications (e.g., thickness, planarity, and the like) for various subsequent processes or applications. Various aspects provide for designing a substrate (e.g., a PCB) incorporating a VSDM, and adjusting one or more aspects of the substrate to design a balanced, ESD-protected substrate. Certain embodiments include molding a substrate having a VSDM layer into a first shape.

Claims

1. A printed circuit board having:

one or more prepreg lavers;

a first region including a voltage switchable dielectric material; and

a flatness within one or more IPC standards for flatness;

a balance region that offsets an imbalance in the printed circuit board associated with the first region.

2. The printed circuit board of claim 1, wherein at least one standard includes a specification associated with IPC-4101A.

3. The printed circuit board of claim 1, wherein a stacking of the prepreg layers is not characterized by mirror symmetry with respect to a centerline associated with the stacking of the prepreg layers.

4. The printed circuit board of claim 1, wherein a stacking of the prepreg layers is not characterized by mirror symmetry with respect to a centerline associated with the printed circuit board.

5. The printed circuit board of claim 1, wherein any of the first region and balance region is substantially planar.

6. The printed circuit board of claim 1, wherein the first region and at least a portion of the balance region are on opposite sides of a centerline of the printed circuit board.

7. The printed circuit board of claim 6, wherein the first region and the portion of the balance region are the same distance from the centerline.

8. The printed circuit board of claim 6, wherein the portion of the balance region is a greater distance from the centerline than the first region.

9. The printed circuit board of claim 1, wherein the first region and at least a portion of the balance region are on the same side of a centerline.

10. The printed circuit board of claim 1, wherein at least a portion of the balance region is a smaller or larger distance from a centerline than the first region.

11. The printed circuit board of claim 1, wherein the first region is characterized by a first thermal expansion coefficient, and the balance region is characterized by a second thermal expansion coefficient.

12. The printed circuit board of claim 1, wherein the balance region includes at least one prepreg layer.

13. The printed circuit board of claim 12, wherein first and second prepreg layers are on the same side of a centerline.

14. The printed circuit board of claim 12, wherein first and second prepreg layers are on opposite sides of a centerline.

15. The printed circuit board of claim 12, wherein a first prepreg layer has a higher resin content than a second prepreg layer.

16. The printed circuit board of claim 12, wherein a first prepreg layer has a larger artwork compensation specification than that of a second prepreg layer.

17. The printed circuit board of claim 12, wherein each of a first and a second prepreg layer is characterized by an artwork compensation specification, and a difference between the artwork compensation specifications is greater than 0.0001 inches per inch of length in a grain direction associated with the respective prepreg layers.

18. The printed circuit board of claim 12, wherein a first prepreg layer has a smaller diameter reinforcement than that of a second prepreg layer.

19. The printed circuit board of claim 12, wherein at least a portion of a reinforcement associated with a first prepreg layer is of a different composition, size, or weave than that associated with a second prepreg layer.

20. The printed circuit board of claim 12, wherein at least one prepreg layer includes a style 106 prepreg layer.

21. The printed circuit board of claim 12, wherein first and second prepreg layers have different thicknesses.

22. The printed circuit board of claim 12, wherein first and second prepreg layers have different basis weights.

23. The printed circuit board of claim 12, wherein the balance region includes a polymer.

24. The printed circuit board of claim 23, wherein the polymer includes a filled polymer.

25. The printed circuit board of claim 24, wherein the filled polymer includes a second voltage switchable dielectric material.