Oxide semiconductor transistors and methods of manufacturing the same

• US 8,399,882 B2
• Filed: 06/11/2010
• Issued: 03/19/2013
• Est. Priority Date: 01/08/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeon, Sang-hun, Song, I-hun, Kim, Chang-jung, Park, Sung-ho
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US12/801,500
• Publication Number:
  US 20110168993A1
• Time in Patent Office: 1,012 Days
• Field of Search: 257/43, 257/76, 257/78, 257/79, 438/30, 438/166
• US Class Current: 257/43
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Transistors and methods of manufacturing the same. A transistor may be an oxide thin film transistor (TFT) with a self-aligned top gate structure. The transistor may include a gate insulating layer between a channel region and a gate electrode that extends from two sides of the gate electrode. The gate insulating layer may cover at least a portion of source and drain regions.

Claims

1. A transistor, comprising:

an oxide semiconductor layer including a source region, a drain region and a channel region, the channel region between the source and drain regions;

a gate electrode on the channel region;

a gate insulating layer between the channel region and the gate electrode, the gate insulating layer on the source region, the drain region, and the channel region; and

insulating spacers on the gate insulating layer and on at least one surface of the gate electrode, the gate insulating layer being wider than a combined width of the gate electrode and the insulating spacers.

2. The transistor of claim 1, further comprising:

an interlayer insulating layer on the oxide semiconductor layer, the gate insulating layer and the gate electrode; and

first and second electrode layers on the interlayer insulating layer and respectively connected to the source and drain regions.

3. The transistor of claim 1, further comprising:

a first electrode layer contacting the source region; and

a second electrode layer contacting the drain region.

4. The transistor of claim 1, wherein the oxide semiconductor layer includes at least one of ZnO, SnO, InO, CdO, SrO, CuO, AlO, GaO, HfO, ZrO, NbO, SmO, GdO, DyO, BaO, TiO, CaO, TaO, LnO, NiO, YO, mixtures thereof, and oxides based thereon.

5. The transistor of claim 4, wherein the oxide semiconductor layer is a ZnO-based oxide.

6. The transistor of claim 5, wherein the ZnO-based oxide includes at least one of indium (In), gallium (Ga), aluminum (Al), titanium (Ti), tin (Sn), zirconium (Zr), hafnium (Hf), yttrium (Y), tantalum (Ta) and chromium (Cr).

7. The transistor of claim 1, wherein the source and drain regions include at least one conductive impurity.

8. The transistor of claim 7, wherein the at least one conductive impurity includes at least one of boron (B), boron difluoride (BF₂), aluminum (Al), gallium (Ga), indium (In) and antimony (Sb).

9. The transistor of claim 1, wherein at least a portion the gate insulating layer has a width greater than a width of the gate electrode and smaller than a width of the oxide semiconductor layer.

10. A transistor, comprising:

an oxide semiconductor layer including a source region, a drain region and a channel region, the channel region between the source and drain regions;

a gate electrode on the channel region;

a gate insulating layer between the channel region and the gate electrode, the gate insulating layer on the source region, the drain region, and the channel region;

a first electrode layer contacting the source region; and

a second electrode layer contacting the drain region, the first and second electrodes contacting at least two sides of the gate insulating layer.

11. The transistor of claim 10, wherein the oxide semiconductor layer includes at least one of ZnO, SnO, InO, CdO, SrO, CuO, AlO, GaO, HfO, ZrO, NbO, SmO, GdO, DyO, BaO, TiO, CaO, TaO, LnO, NiO, YO, mixtures thereof, and oxides based thereon.

12. A method of manufacturing a transistor, the method comprising:

forming an oxide semiconductor layer including a channel region;

forming a gate insulating layer on the oxide semiconductor layer;

forming a conductive layer on the gate insulating layer;

patterning the conductive layer to form a gate electrode corresponding to the channel region and to expose the gate insulating layer adjacent to the gate electrode;

forming source and drain regions in the oxide semiconductor layer adjacent to the gate electrode;

forming insulating spacers on at least one side surface of the gate electrode; and

etching the gate insulating layer by using the gate electrode and the insulating spacers as an etch mask.

13. The method of claim 12, wherein the oxide semiconductor layer includes at least one of ZnO, SnO, InO, CdO, SrO, CuO, AlO, GaO, HfO, ZrO, NbO, SmO, GdO, DyO, BaO, TiO, CaO, TaO, LnO, NiO, YO, mixtures thereof, and oxides based thereon.

14. The method of claim 13, wherein the oxide semiconductor layer includes a ZnO-based oxide.

15. The method of claim 14, wherein the ZnO-based oxide includes at least one of indium (In), gallium (Ga), aluminum (Al), titanium (Ti), tin (Sn), zirconium (Zr), hafnium (Hf), yttrium (Y), tantalum (Ta) and chromium (Cr).

16. The method of claim 12, wherein the forming of the source and drain regions includes injecting at least one conductive impurity into the oxide semiconductor layer through the gate insulating layer adjacent to the gate electrode.

17. The method of claim 16, wherein the at least one conductive impurity includes at least one of boron (B), boron difluoride (BF₂), aluminum (Al), gallium (Ga), indium (In) and antimony (Sb).

18. The method of claim 16, wherein the forming of the source and drain regions includes annealing the oxide semiconductor layer with the at least one conductive impurity at a temperature of less than or equal to about 400°

C.

19. A method of manufacturing a transistor, the method comprising:

forming an oxide semiconductor layer including a channel region;

forming a gate insulating layer on the oxide semiconductor layer;

forming a conductive layer on the gate insulating layer;

patterning the conductive layer to form a gate electrode corresponding to the channel region and to expose the gate insulating layer adjacent to the gate electrode;

forming source and drain regions in the oxide semiconductor layer adjacent to the gate electrode; and

forming first and second electrode layers respectively contacting the source and drain regions, the first and second electrodes contacting at least two sides of the gate insulating layer.

20. The method of claim 19, wherein the oxide semiconductor layer includes at least one of ZnO, SnO, InO, CdO, SrO, CuO, AlO, GaO, HfO, ZrO, NbO, SmO, GdO, DyO, BaO, TiO, CaO, TaO, LnO, NiO, YO, mixtures thereof, and oxides based thereon.