Semiconductor device and method of manufacturing the same

• US 8,399,884 B2
• Filed: 03/25/2011
• Issued: 03/19/2013
• Est. Priority Date: 02/22/2000
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US13/071,759
• Publication Number:
  US 20110169011A1
• Time in Patent Office: 725 Days
• Field of Search: 257/59, 257/72, 257/88, 257/E33.062, 257/E33.053
• US Class Current: 257/59
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133512 Light shielding layers, e.g. black matrix G02F1/136209 takes precedence
• CPC Class Codes: G02F 1/133514 Colour filters
• CPC Class Codes: G02F 1/133784 by rubbing
• CPC Class Codes: G02F 1/13394 spacers regularly patterned on the cell subtrate, e.g. walls, pillars G02F1/133377 takes precedence
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: H01L 2029/7863 with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
• CPC Class Codes: H01L 21/02675 using laser beams
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 : with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 : integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1274 : using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
• CPC Class Codes: H01L 27/1288 : employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/42384 : for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/458 : for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 : for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/786 : Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78621 : with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 : with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H01L 29/78633 : with a light shield
• CPC Class Codes: H01L 29/78645 : with multiple gate
• CPC Class Codes: H01L 29/78675 : with normal-type structure, e.g. with top gate

Abstract

The present invention improves the aperture ratio of a pixel of a reflection-type display device or a reflection type display device without increasing the number of masks and without using a blackmask. A pixel electrode (167) is arranged so as to partially overlap a source wiring (137) for shielding the gap between pixels from light, and a thin film transistor is arranged so as to partially overlap a gate wiring (166) for shielding a channel region of the thin film transistor from light, thereby realizing a high pixel aperture ratio.

Claims

1. A semiconductor device comprising:

a pixel portion comprising;

a first wiring comprising a first conductive layer over a substrate;

a first gate electrode electrically connected to the first wiring, the first gate electrode comprising a second conductive layer over the substrate;

a second gate electrode electrically connected to the first wiring, the second gate electrode comprising a third conductive layer over the substrate;

a second wiring comprising a fourth conductive layer over the substrate, the second wiring being electrically connected to one of a source and a drain of a first transistor; and

a third wiring comprising a fifth conductive layer over the substrate, the third wiring being electrically connected to one of a source and a drain of a second transistor; and

a terminal portion comprising

a fourth wiring comprising a sixth conductive layer,

wherein a first channel formation region of the first transistor and the second conductive layer overlap with each other,

wherein a second channel formation region of the second transistor and the third conductive layer overlap with each other,

wherein the second conductive layer is in direct contact with the first conductive layer through a first contact hole,

wherein the third conductive layer is in direct contact with the first conductive layer through a second contact hole,

wherein the first conductive layer is over and overlapping the fourth conductive layer and the fifth conductive layer, and

wherein the sixth conductive layer and the first conductive layer comprise a same material.

2. The semiconductor device according to claim 1,

wherein the first gate electrode is over the first channel formation region, and

wherein the second gate electrode is over the second channel formation region.

3. The semiconductor device according to claim 1,

wherein the fourth conductive layer is electrically connected to the one of the source and the drain of the first transistor via a seventh conductive layer, and

wherein the fifth conductive layer electrically connected to the one of the source and the drain of the second transistor via an eighth conductive layer.

4. The semiconductor device according to claim 1,

wherein each of the first wiring and the fourth wiring further comprises two conductive layers.

5. The semiconductor device according to claim 1,

wherein the first transistor comprises a first semiconductor layer comprising the first channel formation region, and

wherein the second transistor comprises a second semiconductor layer comprising the second channel formation region.

6. A display device comprising:

a pixel portion comprising;

a first wiring comprising a first conductive layer over a substrate;

a first gate electrode electrically connected to the first wiring, the first gate electrode comprising a second conductive layer over the substrate;

a second gate electrode electrically connected to the first wiring, the second gate electrode comprising a third conductive layer over the substrate;

a second wiring comprising a fourth conductive layer over the substrate, the second wiring being electrically connected to one of a source and a drain of a first transistor;

a third wiring comprising a fifth conductive layer over the substrate, the third wiring being electrically connected to one of a source and a drain of a second transistor;

a first display element electrically connected to the other of the source and the drain of the first transistor; and

a second display element electrically connected to the other of the source and the drain of the second transistor, and

a terminal portion comprising

a fourth wiring comprising a sixth conductive layer,

wherein a first channel formation region of the first transistor and the second conductive layer overlap with each other,

wherein a second channel formation region of the second transistor and the third conductive layer overlap with each other,

wherein the second conductive layer is in direct contact with the first conductive layer through a first contact hole,

wherein the third conductive layer is in direct contact with the first conductive layer through a second contact hole, and

wherein the first conductive layer is over and overlapping the fourth conductive layer and the fifth conductive layer and

wherein the sixth conductive layer and the first conductive layer comprise a same material.

7. The display device according to claim 6,

wherein the first gate electrode is over the first channel formation region, and

wherein the second gate electrode is over the second channel formation region.

8. The display device according to claim 6,

wherein the fourth conductive layer is electrically connected to the one of the source and the drain of the first transistor via a seventh conductive layer, and

wherein the fifth conductive layer is electrically connected to the one of the source and the drain of the second transistor via an eighth conductive layer.

9. The display device according to claim 6, wherein each of the first display element and the second display element comprises a liquid crystal material.

10. The display device according to claim 6,

wherein each of the first wiring and the fourth wiring further comprises two conductive layers.

11. The display device according to claim 6,

wherein the first transistor comprises a first semiconductor layer comprising the first channel formation region, and

wherein the second transistor comprises a second semiconductor layer comprising the second channel formation region.

12. The display device according to claim 6,

wherein the first display element is directly connected to the other of the source and the drain of the first transistor, and

wherein the second display element is directly connected to the other of the source and the drain of the second transistor.

13. A semiconductor device comprising:

a pixel portion comprising;

a first wiring comprising a first conductive layer over a substrate;

a first gate electrode electrically connected to the first wiring, the first gate electrode comprising a second conductive layer over the substrate;

a second gate electrode electrically connected to the first wiring, the second gate electrode comprising a third conductive layer over the substrate;

a second wiring comprising a fourth conductive layer over the substrate, the second wiring being electrically connected to one of a source and a drain of a first transistor; and

a third wiring comprising a fifth conductive layer over the substrate, the third wiring being electrically connected to one of a source and a drain of a second transistor; and

a terminal portion comprising;

a fourth wiring comprising a sixth conductive layer; and

a fifth wiring electrically connected to the fourth wiring, the

fifth wiring comprising a seventh conductive layer,

wherein a first channel formation region of the first transistor and the second conductive layer overlap with each other,

wherein a second channel formation region of the second transistor and the third conductive layer overlap with each other,

wherein the second conductive layer is in direct contact with the first conductive layer through a first contact hole,

wherein the third conductive layer is in direct contact with the first conductive layer through a second contact hole,

wherein the first conductive layer is over and overlapping the fourth conductive layer and the fifth conductive layer,

wherein the sixth conductive layer and the first conductive layer comprise a same first material, and

wherein the seventh conductive layer, the second conductive layer and the third conductive layer comprise a same second material.

14. The semiconductor device according to claim 13,

wherein the first gate electrode is over the first channel formation region, and

wherein the second gate electrode is over the second channel formation region.

15. The semiconductor device according to claim 13,

wherein each of the first wiring and the fourth wiring further comprises two conductive layers.

16. The semiconductor device according to claim 13,

wherein the first transistor comprises a first semiconductor layer comprising the first channel formation region, and

wherein the second transistor comprises a second semiconductor layer comprising the second channel formation region.

17. A display device comprising:

a pixel portion comprising;

a first wiring comprising a first conductive layer over a substrate;

a first gate electrode electrically connected to the first wiring, the first gate electrode comprising a second conductive layer over the substrate;

a second gate electrode electrically connected to the first wiring, the second gate electrode comprising a third conductive layer over the substrate;

a second wiring comprising a fourth conductive layer over the substrate, the second wiring being electrically connected to one of a source and a drain of a first transistor;

a third wiring comprising a fifth conductive layer over the substrate, the third wiring being electrically connected to one of a source and a drain of a second transistor;

a first display element electrically connected to the other of the source and the drain of the first transistor; and

a second display element electrically connected to the other of the source and the drain of the second transistor; and

a terminal portion comprising;

a fourth wiring comprising a sixth conductive layer; and

a fifth wiring electrically connected to the fourth wiring, the

second wiring comprising a seventh conductive layer,

wherein a first channel formation region of the first transistor and the second conductive layer semiconductor film overlap with each other,

wherein a second channel formation region of the second transistor and the third conductive layer overlap with each other,

wherein the second conductive layer is in direct contact with the first conductive layer through a first contact hole,

wherein the third conductive layer is in direct contact with the first conductive layer through a second contact hole,

wherein the first conductive layer is over and overlapping the fourth conductive layer and the fifth conductive layer,

wherein the sixth conductive layer and the first conductive layer comprise a same first material, and

wherein the seventh conductive layer, the second conductive layer and the third conductive layer comprise a same second material.

18. The display device according to claim 17,

wherein the first gate electrode is over the first channel formation region, and

wherein the second gate electrode is over the second channel formation region.

19. The display device according to claim 17,

wherein each of the first display element and the second display element comprises a liquid crystal material.

20. The display device according to claim 17,

wherein each of the first wiring and the fourth wiring further comprises two conductive layers.

21. The display device according to claim 17,

wherein the first transistor comprises a first semiconductor layer comprising the first channel formation region, and

wherein the second transistor comprises a second semiconductor layer comprising the second channel formation region.

22. The display device according to claim 17,

wherein the first display element is directly connected to the other of the source and the drain of the first transistor, and

wherein the second display element is directly connected to the other of the source and the drain of the second transistor.